netdev - Re: [PATCH net-next 5/5] arm64: dts: zynqmp: Add ZCU104 based TSN endpoint

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Message-ID: <CANr-f5yW4sob_fgxhEafHME71QML8K-+Ka5AzNm5p3A0Ktv02Q@mail.gmail.com>
Date:   Tue, 27 Jul 2021 22:10:48 +0200
From:   Gerhard Engleder <gerhard@...leder-embedded.com>
To:     Rob Herring <robh+dt@...nel.org>
Cc:     David Miller <davem@...emloft.net>,
        Jakub Kicinski <kuba@...nel.org>,
        Michal Simek <michal.simek@...inx.com>,
        netdev <netdev@...r.kernel.org>, devicetree@...r.kernel.org
Subject: Re: [PATCH net-next 5/5] arm64: dts: zynqmp: Add ZCU104 based TSN endpoint

On Tue, Jul 27, 2021 at 1:41 AM Rob Herring <robh+dt@...nel.org> wrote:
> > +       compatible = "engleder,zynqmp-tsnep", "xlnx,zynqmp-zcu104-revC",
> > +                    "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
>
> I don't think this will pass schema validation.

You are right. I did rerun the validation and now I see the error.

> In general, do we need a new top-level compatible for every possible
> FPGA image? Shouldn't this be an overlay?

All the devices I have dealt with so far had just a single FPGA image.
There were no dynamic selection of the FPGA image or partial
reconfiguration of the FPGA. So the FPGA image could be seen as part
of the schematics. In this case the FPGA image stuff shall be in the
device tree of the device. For me the question is: Does this combination
of evaluation boards with its own FPGA image form a new device?

The evaluation platform is based on ZCU104. The difference is not
only the FPGA image. Also a FMC extension card with Ethernet PHYs is
needed. So also the physical hardware is different.

>From my point of view it is a separate hardware platform with its own
device tree. It's purpose is to show two tsnep Ethernet controllers in
action. So far it worked good for me to see the FPGA image as part of
the schematics like the list of devices on the SPI bus. No special handling
just because an FPGA is used, which in the end is not relevant for the
software because software cannot and need not differentiate between
normal hardware and FPGA based hardware.

But I also understand the view of just another FPGA image for an existing
hardware.

My goal is to get all necessary stuff, which is needed to run the evaluation
platform, into mainline. I must confess, I have not thought about using an
overlay. Is it right that overlays are not part of the kernel tree?

Gerhard