netdev - Re: [PATCH 07/14] bpf/tests: Add more ALU64 BPF

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Date:   Wed, 28 Jul 2021 16:32:27 -0700
From:   Yonghong Song <yhs@...com>
To:     Johan Almbladh <johan.almbladh@...finetworks.com>,
        <ast@...nel.org>, <daniel@...earbox.net>, <andrii@...nel.org>
CC:     <kafai@...com>, <songliubraving@...com>,
        <john.fastabend@...il.com>, <kpsingh@...nel.org>,
        <Tony.Ambardar@...il.com>, <netdev@...r.kernel.org>,
        <bpf@...r.kernel.org>
Subject: Re: [PATCH 07/14] bpf/tests: Add more ALU64 BPF_MUL tests



On 7/28/21 10:04 AM, Johan Almbladh wrote:
> This patch adds BPF_MUL tests for 64x32 and 64x64 multiply. Mainly
> testing 32-bit JITs that implement ALU64 operations with two 32-bit
> CPU registers per operand.
> 
> Signed-off-by: Johan Almbladh <johan.almbladh@...finetworks.com>
> ---
>   lib/test_bpf.c | 48 ++++++++++++++++++++++++++++++++++++++++++++++++
>   1 file changed, 48 insertions(+)
> 
> diff --git a/lib/test_bpf.c b/lib/test_bpf.c
> index b930fa35b9ef..eb61088a674f 100644
> --- a/lib/test_bpf.c
> +++ b/lib/test_bpf.c
> @@ -3051,6 +3051,31 @@ static struct bpf_test tests[] = {
>   		{ },
>   		{ { 0, 2147483647 } },
>   	},
> +	{
> +		"ALU64_MUL_X: 64x64 multiply, low word",
> +		.u.insns_int = {
> +			BPF_LD_IMM64(R0, 0x0fedcba987654321LL),
> +			BPF_LD_IMM64(R1, 0x123456789abcdef0LL),
> +			BPF_ALU64_REG(BPF_MUL, R0, R1),
> +			BPF_EXIT_INSN(),
> +		},
> +		INTERNAL,
> +		{ },
> +		{ { 0, 0xe5618cf0 } }

Same here. Maybe capture the true 64-bit R0 value?

> +	},
> +	{
> +		"ALU64_MUL_X: 64x64 multiply, high word",
> +		.u.insns_int = {
> +			BPF_LD_IMM64(R0, 0x0fedcba987654321LL),
> +			BPF_LD_IMM64(R1, 0x123456789abcdef0LL),
> +			BPF_ALU64_REG(BPF_MUL, R0, R1),
> +			BPF_ALU64_IMM(BPF_RSH, R0, 32),
> +			BPF_EXIT_INSN(),
> +		},
> +		INTERNAL,
> +		{ },
> +		{ { 0, 0x2236d88f } }
> +	},
>   	/* BPF_ALU | BPF_MUL | BPF_K */
>   	{
>   		"ALU_MUL_K: 2 * 3 = 6",
> @@ -3161,6 +3186,29 @@ static struct bpf_test tests[] = {
>   		{ },
>   		{ { 0, 0x1 } },
>   	},
> +	{
> +		"ALU64_MUL_K: 64x32 multiply, low word",
> +		.u.insns_int = {
> +			BPF_LD_IMM64(R0, 0x0123456789abcdefLL),
> +			BPF_ALU64_IMM(BPF_MUL, R0, 0x12345678),
> +			BPF_EXIT_INSN(),
> +		},
> +		INTERNAL,
> +		{ },
> +		{ { 0, 0xe242d208 } }
> +	},
> +	{
> +		"ALU64_MUL_K: 64x32 multiply, high word",
> +		.u.insns_int = {
> +			BPF_LD_IMM64(R0, 0x0123456789abcdefLL),
> +			BPF_ALU64_IMM(BPF_MUL, R0, 0x12345678),
> +			BPF_ALU64_IMM(BPF_RSH, R0, 32),
> +			BPF_EXIT_INSN(),
> +		},
> +		INTERNAL,
> +		{ },
> +		{ { 0, 0xc28f5c28 } }
> +	},
>   	/* BPF_ALU | BPF_DIV | BPF_X */
>   	{
>   		"ALU_DIV_X: 6 / 2 = 3",
>