Message-ID: <326af2cb-1796-f10b-06a6-8494d52f2387@xilinx.com>
Date:   Thu, 29 Jul 2021 09:57:19 +0200
From:   Michal Simek <michal.simek@...inx.com>
To:     Gerhard Engleder <gerhard@...leder-embedded.com>,
        Michal Simek <michal.simek@...inx.com>
CC:     Rob Herring <robh+dt@...nel.org>,
        David Miller <davem@...emloft.net>,
        Jakub Kicinski <kuba@...nel.org>,
        netdev <netdev@...r.kernel.org>, <devicetree@...r.kernel.org>
Subject: Re: [PATCH net-next 2/5] dt-bindings: net: Add tsnep Ethernet
 controller



On 7/29/21 9:07 AM, Gerhard Engleder wrote:
> On Thu, Jul 29, 2021 at 7:07 AM Michal Simek <michal.simek@...inx.com> wrote:
>> On 7/28/21 10:14 PM, Gerhard Engleder wrote:
>>> On Wed, Jul 28, 2021 at 12:55 PM Michal Simek <michal.simek@...inx.com> wrote:
>>>>>>>>>> +      - enum:
>>>>>>>>>> +        - engleder,tsnep
>>>>>>>>>
>>>>>>>>> tsnep is pretty generic. Only 1 version ever? Or differences are/will
>>>>>>>>> be discoverable by other means.
>>>>>>>>
>>>>>>>> Differences shall be detected by flags in the registers; e.g., a flag for
>>>>>>>> gate control support. Anyway a version may make sense. Can you
>>>>>>>> point to a good reference binding with versions? I did not find a
>>>>>>>> network controller binding with versions.
>>>>>>>
>>>>>>> Some of the SiFive IP blocks have versions. Version numbers are the
>>>>>>> exception though. Ideally they would correspond to some version of
>>>>>>> your FPGA image. I just don't want to see 'v1' because that sounds
>>>>>>> made up. The above string can mean 'v1' or whatever version you want.
>>>>>>> I'm fine if you just add some description here about feature flag
>>>>>>> registers.
>>>>>>
>>>>>> Don't Xilinx design tool (vivado) force you to use IP version?
>>>>>> Normally all Xilinx IPs have certain version because that's the only way
>>>>>> how to manage it.
>>>>>
>>>>> Yes I use an IP version in the Xilinx design tool. I use it as a version of the
>>>>> VHDL code itself. In my case this version is not related to the
>>>>> hardware software
>>>>> interface. The goal is to keep the hardware software interface compatible, so
>>>>> the IP version should not be relevant.
>>>>
>>>> I expect this is goal for everybody but it fails over time. We normally
>>>> compose compatible string for PL based IP with IP version which is used.
>>>> And it is quite common that couple of HW version are SW compatible to
>>>> each other.
>>>> It means use the same HW version as you use now. When you reach the
>>>> point when your HW IP needs to be upgraded and will require SW alignment
>>>> you have versions around which can be used directly.
>>>
>>> I would like to follow the argument from Rob:
>>> "The above string can mean 'v1' or whatever version you want."
>>> If there ever is an incompatible new IP version, then a new compatible string
>>> can be added which means 'v2'. E.g. for 128bit physical address support I
>>> would choose the compatible string 'engleder,tsnep128'. I don't see an
>>> advantage in adding a version number to the compatible string.
>>>
>>> This IP will be used in products where compatible hardware is a must.
>>> An IP upgrade which requires SW alignment will result in heavy complaints
>>> from the customers. Such an IP upgrade would result in a new IP.
>>> Like for shared libraries, an incompatible API change is similar to a new
>>> library.
>>
>> From my point of view where I expect the most of customers are using
>> Xilinx DTG (device tree generator) compatible string is composed with IP
>> name and version used in design tool. This is unique combination which
>> properly describes your HW.
>> And choosing different compatible string or string without version is
>> breaking this connection between hw design tool and sw.
>>
>> From my perspective it is much simpler to understand that your HW ip
>> called ABC-rev1 requires DT node which is your_company,ABC-rev1 instead
>> of any made name.
>> But up2you - you will be talking to your customers.
> 
> Thanks for explaining your point of view. From my side I don't expect that
> Xilinx DTG is used. The few people I know who are working with Zynq/ZynqMP
> are using the Xilinx tools only to generate the bitstream. This way you are able
> to do software development for the Zynq/ZynqMP like for any other hardware
> platform.

Definitely possible but when you have 20 soft IPs if you are not using
DTG you have big issue to have proper IRQ ids, memory maps and make
sense to use DTG to give you that initial description which you can tune
by hand. But it is decent starting point.
Maybe in your TSN case you are dealing just with small number of IPs
that's this is easy to do by hand.

Thanks,
Michal

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