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Date:   Tue, 3 Aug 2021 16:29:13 +0200
From:   Andrew Lunn <andrew@...n.ch>
To:     Oleksij Rempel <o.rempel@...gutronix.de>
Cc:     Vladimir Oltean <olteanv@...il.com>,
        Vivien Didelot <vivien.didelot@...il.com>,
        Florian Fainelli <f.fainelli@...il.com>,
        "David S. Miller" <davem@...emloft.net>,
        Jakub Kicinski <kuba@...nel.org>,
        Russell King <linux@...linux.org.uk>,
        Pengutronix Kernel Team <kernel@...gutronix.de>,
        netdev@...r.kernel.org, linux-kernel@...r.kernel.org,
        linux-mips@...r.kernel.org
Subject: Re: [PATCH net v2 1/1] net: dsa: qca: ar9331: make proper initial
 port defaults

On Tue, Aug 03, 2021 at 11:54:19AM +0200, Oleksij Rempel wrote:
> On Tue, Aug 03, 2021 at 12:06:05PM +0300, Vladimir Oltean wrote:
> > On Tue, Aug 03, 2021 at 10:53:20AM +0200, Oleksij Rempel wrote:
> > > Make sure that all external port are actually isolated from each other,
> > > so no packets are leaked.
> > > 
> > > Fixes: ec6698c272de ("net: dsa: add support for Atheros AR9331 built-in switch")
> > > Signed-off-by: Oleksij Rempel <o.rempel@...gutronix.de>
> > > ---
> > > changes v2:
> > > - do not enable address learning by default
> > > 
> > >  drivers/net/dsa/qca/ar9331.c | 98 +++++++++++++++++++++++++++++++++++-
> > >  1 file changed, 97 insertions(+), 1 deletion(-)
> > > 
> > > diff --git a/drivers/net/dsa/qca/ar9331.c b/drivers/net/dsa/qca/ar9331.c
> > > index 6686192e1883..de7c06b6c85f 100644
> > > --- a/drivers/net/dsa/qca/ar9331.c
> > > +++ b/drivers/net/dsa/qca/ar9331.c
> > > @@ -101,6 +101,46 @@
> > >  	 AR9331_SW_PORT_STATUS_RX_FLOW_EN | AR9331_SW_PORT_STATUS_TX_FLOW_EN | \
> > >  	 AR9331_SW_PORT_STATUS_SPEED_M)
> > >  
> > > +#define AR9331_SW_REG_PORT_CTRL(_port)			(0x104 + (_port) * 0x100)
> > > +#define AR9331_SW_PORT_CTRL_ING_MIRROR_EN		BIT(17)
> > > +#define AR9331_SW_PORT_CTRL_LOCK_DROP_EN		BIT(5)
> > 
> > not used
> 
> ack, will remove

Just expanding Vladimirs comment. Patches for net should be as minimal
as possible, so they are obviously correct.

   Andrew

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