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Message-ID: <CAFBinCAVaaXd+jXBtA9RETP5AavOfeUVZLkU1ohGT2Lmx+H1cw@mail.gmail.com>
Date: Tue, 3 Aug 2021 22:45:13 +0200
From: Martin Blumenstingl <martin.blumenstingl@...glemail.com>
To: Anand Moon <linux.amoon@...il.com>
Cc: netdev@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
linux-amlogic@...ts.infradead.org, linux-kernel@...r.kernel.org,
linux-stm32@...md-mailman.stormreply.com,
devicetree@...r.kernel.org, Jerome Brunet <jbrunet@...libre.com>,
Neil Armstrong <narmstrong@...libre.com>,
Rob Herring <robh+dt@...nel.org>,
Kevin Hilman <khilman@...libre.com>,
Giuseppe Cavallaro <peppe.cavallaro@...com>,
Alexandre Torgue <alexandre.torgue@...s.st.com>,
Jose Abreu <joabreu@...opsys.com>,
"David S. Miller" <davem@...emloft.net>,
Jakub Kicinski <kuba@...nel.org>,
Maxime Coquelin <mcoquelin.stm32@...il.com>,
Philipp Zabel <p.zabel@...gutronix.de>,
Emiliano Ingrassia <ingrassia@...genesys.com>
Subject: Re: [PATCHv1 3/3] net: stmmac: dwmac-meson8b: Add reset controller
for ethernet phy
Hi Anand,
On Thu, Jul 29, 2021 at 10:11 PM Anand Moon <linux.amoon@...il.com> wrote:
>
> Add reset controller for Ethernet phy reset on every boot for
> Amlogic SoC.
I think this description does not match what's going on inside the SoC:
- for all SoCs earlier than GXL the PHY is external so the reset for
the PHY is a GPIO
- the reset line you are passing in the .dts belongs to the Ethernet
controller on SoCs earlier than GXL
- I *believe* that the rset line which you're passing in the .dts
belongs to the Ethernet controller AND the built-in MDIO mux on GXL
and newer, see also [0]
- from how the PRG_ETH registers work I doubt that these are connected
to a reset line (as they're managing mostly delays and protocol - so I
don't see what would be reset). This is speculation though.
Best regards,
Martin
[0] https://lore.kernel.org/linux-amlogic/553e127c-9839-d15b-d435-c01f18c7be48@gmail.com/
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