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Date:   Tue, 3 Aug 2021 22:45:13 +0200
From:   Martin Blumenstingl <>
To:     Anand Moon <>
Cc:,,,,,, Jerome Brunet <>,
        Neil Armstrong <>,
        Rob Herring <>,
        Kevin Hilman <>,
        Giuseppe Cavallaro <>,
        Alexandre Torgue <>,
        Jose Abreu <>,
        "David S. Miller" <>,
        Jakub Kicinski <>,
        Maxime Coquelin <>,
        Philipp Zabel <>,
        Emiliano Ingrassia <>
Subject: Re: [PATCHv1 3/3] net: stmmac: dwmac-meson8b: Add reset controller
 for ethernet phy

Hi Anand,

On Thu, Jul 29, 2021 at 10:11 PM Anand Moon <> wrote:
> Add reset controller for Ethernet phy reset on every boot for
> Amlogic SoC.
I think this description does not match what's going on inside the SoC:
- for all SoCs earlier than GXL the PHY is external so the reset for
the PHY is a GPIO
- the reset line you are passing in the .dts belongs to the Ethernet
controller on SoCs earlier than GXL
- I *believe* that the rset line which you're passing in the .dts
belongs to the Ethernet controller AND the built-in MDIO mux on GXL
and newer, see also [0]
- from how the PRG_ETH registers work I doubt that these are connected
to a reset line (as they're managing mostly delays and protocol - so I
don't see what would be reset). This is speculation though.

Best regards,


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