netdev - RE: [PATCH net-next 2/2] r8169: change the L0/L1 entrance latencies for RTL8106e

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Message-ID: <95d8ea6b2b814bb9932961360ccd2061@realtek.com>
Date:   Sat, 7 Aug 2021 03:50:47 +0000
From:   Hayes Wang <hayeswang@...ltek.com>
To:     Heiner Kallweit <hkallweit1@...il.com>
CC:     "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
        nic_swsd <nic_swsd@...ltek.com>,
        "koba.ko@...onical.com" <koba.ko@...onical.com>
Subject: RE: [PATCH net-next 2/2] r8169: change the L0/L1 entrance latencies for RTL8106e

Heiner Kallweit <hkallweit1@...il.com>
> Sent: Saturday, August 7, 2021 5:28 AM
[...]
> Most chip versions use rtl_set_def_aspm_entry_latency() that sets
> the value to 0x27. Does this value also work for RTL8106e?

No, it doesn't work.

> Can you explain how the L0 and L1 times in us map to the
> register value? Then we could add a function that doesn't work
> with a magic value but takes the L0 and L1 times in us as
> parameter.

L0 (bit 0~2):
	0: 1us
	1: 2us
	2: 3us
	3: 4us
	4: 5us
	5: 6us
	6: 7us
	7: 7us (The maximum is 7us)

L1 (bit 3~5):
	0: 1us
	1: 2us
	2: 4us
	3: 8us
	4: 16us
	5: 32us
	6: 64us
	7: 64us (The maximum is 64us)

Best Regards,
Hayes