netdev - Re: [RFC PATCH net-next 2/4] net: dsa: remove the "dsa_to_port in a loop" antipattern from the core

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Date:   Wed, 11 Aug 2021 01:04:47 +0800
From:   DENG Qingfang <dqfext@...il.com>
To:     Vladimir Oltean <olteanv@...il.com>
Cc:     Florian Fainelli <f.fainelli@...il.com>,
        Vladimir Oltean <vladimir.oltean@....com>,
        netdev@...r.kernel.org, Jakub Kicinski <kuba@...nel.org>,
        "David S. Miller" <davem@...emloft.net>,
        Andrew Lunn <andrew@...n.ch>,
        Vivien Didelot <vivien.didelot@...il.com>,
        Kurt Kanzenbach <kurt@...utronix.de>,
        Woojung Huh <woojung.huh@...rochip.com>,
        UNGLinuxDriver@...rochip.com, Sean Wang <sean.wang@...iatek.com>,
        Landen Chao <Landen.Chao@...iatek.com>,
        Matthias Brugger <matthias.bgg@...il.com>,
        Claudiu Manoil <claudiu.manoil@....com>,
        Alexandre Belloni <alexandre.belloni@...tlin.com>,
        George McCollister <george.mccollister@...il.com>
Subject: Re: [RFC PATCH net-next 2/4] net: dsa: remove the "dsa_to_port in a loop" antipattern from the core

On Tue, Aug 10, 2021 at 07:35:33PM +0300, Vladimir Oltean wrote:
> If I were to guess where Qingfang was hinting at, is that the receive
> path now needs to iterate over a list, whereas before it simply indexed
> an array:
> 
> static inline struct net_device *dsa_master_find_slave(struct net_device *dev,
> 						       int device, int port)
> {
> 	struct dsa_port *cpu_dp = dev->dsa_ptr;
> 	struct dsa_switch_tree *dst = cpu_dp->dst;
> 	struct dsa_port *dp;
> 
> 	list_for_each_entry(dp, &dst->ports, list)
> 		if (dp->ds->index == device && dp->index == port &&
> 		    dp->type == DSA_PORT_TYPE_USER)
> 			return dp->slave;
> 
> 	return NULL;
> }
> 
> I will try in the following days to make a prototype implementation of
> converting back the linked list into an array and see if there is any
> justifiable performance improvement.
> 
> [ even if this would make the "multiple CPU ports in LAG" implementation
>   harder ]

Yes, you got my point.

There is RTL8390M series SoC, which has 52+ ports but a weak CPU (MIPS
34kc 700MHz). In that case the linear lookup time and the potential cache
miss could make a difference.