| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Date: Fri, 13 Aug 2021 20:26:21 +0000
From: Michael Kelley <mikelley@...rosoft.com>
To: Tianyu Lan <ltykernel@...il.com>,
KY Srinivasan <kys@...rosoft.com>,
Haiyang Zhang <haiyangz@...rosoft.com>,
Stephen Hemminger <sthemmin@...rosoft.com>,
"wei.liu@...nel.org" <wei.liu@...nel.org>,
Dexuan Cui <decui@...rosoft.com>,
"tglx@...utronix.de" <tglx@...utronix.de>,
"mingo@...hat.com" <mingo@...hat.com>,
"bp@...en8.de" <bp@...en8.de>, "x86@...nel.org" <x86@...nel.org>,
"hpa@...or.com" <hpa@...or.com>,
"dave.hansen@...ux.intel.com" <dave.hansen@...ux.intel.com>,
"luto@...nel.org" <luto@...nel.org>,
"peterz@...radead.org" <peterz@...radead.org>,
"konrad.wilk@...cle.com" <konrad.wilk@...cle.com>,
"boris.ostrovsky@...cle.com" <boris.ostrovsky@...cle.com>,
"jgross@...e.com" <jgross@...e.com>,
"sstabellini@...nel.org" <sstabellini@...nel.org>,
"joro@...tes.org" <joro@...tes.org>,
"will@...nel.org" <will@...nel.org>,
"davem@...emloft.net" <davem@...emloft.net>,
"kuba@...nel.org" <kuba@...nel.org>,
"jejb@...ux.ibm.com" <jejb@...ux.ibm.com>,
"martin.petersen@...cle.com" <martin.petersen@...cle.com>,
"arnd@...db.de" <arnd@...db.de>, "hch@....de" <hch@....de>,
"m.szyprowski@...sung.com" <m.szyprowski@...sung.com>,
"robin.murphy@....com" <robin.murphy@....com>,
"thomas.lendacky@....com" <thomas.lendacky@....com>,
"brijesh.singh@....com" <brijesh.singh@....com>,
"ardb@...nel.org" <ardb@...nel.org>,
Tianyu Lan <Tianyu.Lan@...rosoft.com>,
"pgonda@...gle.com" <pgonda@...gle.com>,
"martin.b.radev@...il.com" <martin.b.radev@...il.com>,
"akpm@...ux-foundation.org" <akpm@...ux-foundation.org>,
"kirill.shutemov@...ux.intel.com" <kirill.shutemov@...ux.intel.com>,
"rppt@...nel.org" <rppt@...nel.org>,
"sfr@...b.auug.org.au" <sfr@...b.auug.org.au>,
"saravanand@...com" <saravanand@...com>,
"krish.sadhukhan@...cle.com" <krish.sadhukhan@...cle.com>,
"aneesh.kumar@...ux.ibm.com" <aneesh.kumar@...ux.ibm.com>,
"xen-devel@...ts.xenproject.org" <xen-devel@...ts.xenproject.org>,
"rientjes@...gle.com" <rientjes@...gle.com>,
"hannes@...xchg.org" <hannes@...xchg.org>,
"tj@...nel.org" <tj@...nel.org>
CC: "iommu@...ts.linux-foundation.org" <iommu@...ts.linux-foundation.org>,
"linux-arch@...r.kernel.org" <linux-arch@...r.kernel.org>,
"linux-hyperv@...r.kernel.org" <linux-hyperv@...r.kernel.org>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>,
"linux-scsi@...r.kernel.org" <linux-scsi@...r.kernel.org>,
"netdev@...r.kernel.org" <netdev@...r.kernel.org>,
vkuznets <vkuznets@...hat.com>,
"parri.andrea@...il.com" <parri.andrea@...il.com>,
"dave.hansen@...el.com" <dave.hansen@...el.com>
Subject: RE: [PATCH V3 05/13] HV: Add Write/Read MSR registers via ghcb page
From: Michael Kelley <mikelley@...rosoft.com> Sent: Friday, August 13, 2021 12:31 PM
> To: Tianyu Lan <ltykernel@...il.com>; KY Srinivasan <kys@...rosoft.com>; Haiyang Zhang <haiyangz@...rosoft.com>;
> Stephen Hemminger <sthemmin@...rosoft.com>; wei.liu@...nel.org; Dexuan Cui <decui@...rosoft.com>;
> tglx@...utronix.de; mingo@...hat.com; bp@...en8.de; x86@...nel.org; hpa@...or.com; dave.hansen@...ux.intel.com;
> luto@...nel.org; peterz@...radead.org; konrad.wilk@...cle.com; boris.ostrovsky@...cle.com; jgross@...e.com;
> sstabellini@...nel.org; joro@...tes.org; will@...nel.org; davem@...emloft.net; kuba@...nel.org; jejb@...ux.ibm.com;
> martin.petersen@...cle.com; arnd@...db.de; hch@....de; m.szyprowski@...sung.com; robin.murphy@....com;
> thomas.lendacky@....com; brijesh.singh@....com; ardb@...nel.org; Tianyu Lan <Tianyu.Lan@...rosoft.com>;
> pgonda@...gle.com; martin.b.radev@...il.com; akpm@...ux-foundation.org; kirill.shutemov@...ux.intel.com;
> rppt@...nel.org; sfr@...b.auug.org.au; saravanand@...com; krish.sadhukhan@...cle.com;
> aneesh.kumar@...ux.ibm.com; xen-devel@...ts.xenproject.org; rientjes@...gle.com; hannes@...xchg.org;
> tj@...nel.org
> Cc: iommu@...ts.linux-foundation.org; linux-arch@...r.kernel.org; linux-hyperv@...r.kernel.org; linux-
> kernel@...r.kernel.org; linux-scsi@...r.kernel.org; netdev@...r.kernel.org; vkuznets <vkuznets@...hat.com>;
> parri.andrea@...il.com; dave.hansen@...el.com
> Subject: RE: [PATCH V3 05/13] HV: Add Write/Read MSR registers via ghcb page
>
> From: Tianyu Lan <ltykernel@...il.com> Sent: Monday, August 9, 2021 10:56 AM
> > Subject: [PATCH V3 05/13] HV: Add Write/Read MSR registers via ghcb page
>
> See previous comments about tag in the Subject line.
>
> > Hyper-V provides GHCB protocol to write Synthetic Interrupt
> > Controller MSR registers in Isolation VM with AMD SEV SNP
> > and these registers are emulated by hypervisor directly.
> > Hyper-V requires to write SINTx MSR registers twice. First
> > writes MSR via GHCB page to communicate with hypervisor
> > and then writes wrmsr instruction to talk with paravisor
> > which runs in VMPL0. Guest OS ID MSR also needs to be set
> > via GHCB.
> >
> > Signed-off-by: Tianyu Lan <Tianyu.Lan@...rosoft.com>
> > ---
> > Change since v1:
> > * Introduce sev_es_ghcb_hv_call_simple() and share code
> > between SEV and Hyper-V code.
> > ---
> > arch/x86/hyperv/hv_init.c | 33 ++-------
> > arch/x86/hyperv/ivm.c | 110 +++++++++++++++++++++++++++++
> > arch/x86/include/asm/mshyperv.h | 78 +++++++++++++++++++-
> > arch/x86/include/asm/sev.h | 3 +
> > arch/x86/kernel/cpu/mshyperv.c | 3 +
> > arch/x86/kernel/sev-shared.c | 63 ++++++++++-------
> > drivers/hv/hv.c | 121 ++++++++++++++++++++++----------
> > include/asm-generic/mshyperv.h | 12 +++-
> > 8 files changed, 329 insertions(+), 94 deletions(-)
> >
> > diff --git a/arch/x86/hyperv/hv_init.c b/arch/x86/hyperv/hv_init.c
> > index b3683083208a..ab0b33f621e7 100644
> > --- a/arch/x86/hyperv/hv_init.c
> > +++ b/arch/x86/hyperv/hv_init.c
> > @@ -423,7 +423,7 @@ void __init hyperv_init(void)
> > goto clean_guest_os_id;
> >
> > if (hv_isolation_type_snp()) {
> > - ms_hyperv.ghcb_base = alloc_percpu(void *);
> > + ms_hyperv.ghcb_base = alloc_percpu(union hv_ghcb __percpu *);
>
> union hv_ghcb isn't defined. It is not added until patch 6 of the series.
>
Ignore this comment. My mistake.
Michael
Powered by blists - more mailing lists