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Message-ID: <1629291717-38564-3-git-send-email-liudongdong3@huawei.com>
Date: Wed, 18 Aug 2021 21:01:51 +0800
From: Dongdong Liu <liudongdong3@...wei.com>
To: <helgaas@...nel.org>, <hch@...radead.org>, <kw@...ux.com>,
<logang@...tatee.com>, <leon@...nel.org>,
<linux-pci@...r.kernel.org>, <rajur@...lsio.com>,
<hverkuil-cisco@...all.nl>
CC: <linux-media@...r.kernel.org>, <netdev@...r.kernel.org>
Subject: [PATCH V8 2/8] PCI: Use cached Device Capabilities 2 Register
It will make sense to store the pcie_devcap2 value in the pci_dev
structure instead of reading Device Capabilities 2 Register multiple
times. Get the pcie_devcap2 value set_pcie_port_type(), then use
cached pcie_devcap2 in the needed place.
Signed-off-by: Dongdong Liu <liudongdong3@...wei.com>
Reviewed-by: Christoph Hellwig <hch@....de>
---
drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c | 4 +---
drivers/pci/pci.c | 9 ++++-----
drivers/pci/probe.c | 10 ++++------
include/linux/pci.h | 2 ++
4 files changed, 11 insertions(+), 14 deletions(-)
diff --git a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
index dbf9a0e..a8e1e22 100644
--- a/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
+++ b/drivers/net/ethernet/chelsio/cxgb4/cxgb4_main.c
@@ -6304,7 +6304,6 @@ static int cxgb4_iov_configure(struct pci_dev *pdev, int num_vfs)
struct pci_dev *pbridge;
struct port_info *pi;
char name[IFNAMSIZ];
- u32 devcap2;
u16 flags;
/* If we want to instantiate Virtual Functions, then our
@@ -6314,10 +6313,9 @@ static int cxgb4_iov_configure(struct pci_dev *pdev, int num_vfs)
*/
pbridge = pdev->bus->self;
pcie_capability_read_word(pbridge, PCI_EXP_FLAGS, &flags);
- pcie_capability_read_dword(pbridge, PCI_EXP_DEVCAP2, &devcap2);
if ((flags & PCI_EXP_FLAGS_VERS) < 2 ||
- !(devcap2 & PCI_EXP_DEVCAP2_ARI)) {
+ !(pbridge->pcie_devcap2 & PCI_EXP_DEVCAP2_ARI)) {
/* Our parent bridge does not support ARI so issue a
* warning and skip instantiating the VFs. They
* won't be reachable.
diff --git a/drivers/pci/pci.c b/drivers/pci/pci.c
index dc3bfb2..d14c573 100644
--- a/drivers/pci/pci.c
+++ b/drivers/pci/pci.c
@@ -3700,7 +3700,7 @@ int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask)
{
struct pci_bus *bus = dev->bus;
struct pci_dev *bridge;
- u32 cap, ctl2;
+ u32 ctl2;
if (!pci_is_pcie(dev))
return -EINVAL;
@@ -3724,19 +3724,18 @@ int pci_enable_atomic_ops_to_root(struct pci_dev *dev, u32 cap_mask)
while (bus->parent) {
bridge = bus->self;
- pcie_capability_read_dword(bridge, PCI_EXP_DEVCAP2, &cap);
-
switch (pci_pcie_type(bridge)) {
/* Ensure switch ports support AtomicOp routing */
case PCI_EXP_TYPE_UPSTREAM:
case PCI_EXP_TYPE_DOWNSTREAM:
- if (!(cap & PCI_EXP_DEVCAP2_ATOMIC_ROUTE))
+ if (!(bridge->pcie_devcap2 &
+ PCI_EXP_DEVCAP2_ATOMIC_ROUTE))
return -EINVAL;
break;
/* Ensure root port supports all the sizes we care about */
case PCI_EXP_TYPE_ROOT_PORT:
- if ((cap & cap_mask) != cap_mask)
+ if ((bridge->pcie_devcap2 & cap_mask) != cap_mask)
return -EINVAL;
break;
}
diff --git a/drivers/pci/probe.c b/drivers/pci/probe.c
index cc700f6..c83245b 100644
--- a/drivers/pci/probe.c
+++ b/drivers/pci/probe.c
@@ -1500,6 +1500,7 @@ void set_pcie_port_type(struct pci_dev *pdev)
pdev->pcie_flags_reg = reg16;
pci_read_config_dword(pdev, pos + PCI_EXP_DEVCAP, &pdev->pcie_devcap);
pdev->pcie_mpss = pdev->pcie_devcap & PCI_EXP_DEVCAP_PAYLOAD;
+ pci_read_config_dword(pdev, pos + PCI_EXP_DEVCAP2, &pdev->pcie_devcap2);
parent = pci_upstream_bridge(pdev);
if (!parent)
@@ -2116,7 +2117,7 @@ static void pci_configure_ltr(struct pci_dev *dev)
#ifdef CONFIG_PCIEASPM
struct pci_host_bridge *host = pci_find_host_bridge(dev->bus);
struct pci_dev *bridge;
- u32 cap, ctl;
+ u32 ctl;
if (!pci_is_pcie(dev))
return;
@@ -2124,8 +2125,7 @@ static void pci_configure_ltr(struct pci_dev *dev)
/* Read L1 PM substate capabilities */
dev->l1ss = pci_find_ext_capability(dev, PCI_EXT_CAP_ID_L1SS);
- pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
- if (!(cap & PCI_EXP_DEVCAP2_LTR))
+ if (!(dev->pcie_devcap2 & PCI_EXP_DEVCAP2_LTR))
return;
pcie_capability_read_dword(dev, PCI_EXP_DEVCTL2, &ctl);
@@ -2165,13 +2165,11 @@ static void pci_configure_eetlp_prefix(struct pci_dev *dev)
#ifdef CONFIG_PCI_PASID
struct pci_dev *bridge;
int pcie_type;
- u32 cap;
if (!pci_is_pcie(dev))
return;
- pcie_capability_read_dword(dev, PCI_EXP_DEVCAP2, &cap);
- if (!(cap & PCI_EXP_DEVCAP2_EE_PREFIX))
+ if (!(dev->pcie_devcap2 & PCI_EXP_DEVCAP2_EE_PREFIX))
return;
pcie_type = pci_pcie_type(dev);
diff --git a/include/linux/pci.h b/include/linux/pci.h
index aee7c85..9aab67f 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -341,6 +341,8 @@ struct pci_dev {
u8 pin; /* Interrupt pin this device uses */
u16 pcie_flags_reg; /* Cached PCIe Capabilities Register */
u32 pcie_devcap; /* Cached Device Capabilities Register */
+ u32 pcie_devcap2; /* Cached Device Capabilities 2
+ Register */
unsigned long *dma_alias_mask;/* Mask of enabled devfn aliases */
struct pci_driver *driver; /* Driver bound to this device */
--
2.7.4
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