netdev - Re: [RFC PATCH net-next 4/5] net: dsa: realtek-smi: add rtl8365mb subdriver for RTL8365MB-VC

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Message-Id: <20210823043725.163922-1-dqfext@gmail.com>
Date:   Mon, 23 Aug 2021 12:37:25 +0800
From:   DENG Qingfang <dqfext@...il.com>
To:     Alvin Šipraga <alvin@...s.dk>
Cc:     Linus Walleij <linus.walleij@...aro.org>,
        Andrew Lunn <andrew@...n.ch>,
        Vivien Didelot <vivien.didelot@...il.com>,
        Florian Fainelli <f.fainelli@...il.com>,
        Vladimir Oltean <olteanv@...il.com>,
        "David S. Miller" <davem@...emloft.net>,
        Jakub Kicinski <kuba@...nel.org>,
        Rob Herring <robh+dt@...nel.org>,
        Heiner Kallweit <hkallweit1@...il.com>,
        Russell King <linux@...linux.org.uk>, mir@...g-olufsen.dk,
        Alvin Šipraga <alsi@...g-olufsen.dk>,
        netdev@...r.kernel.org, devicetree@...r.kernel.org,
        linux-kernel@...r.kernel.org
Subject: Re: [RFC PATCH net-next 4/5] net: dsa: realtek-smi: add rtl8365mb subdriver for RTL8365MB-VC

On Sun, Aug 22, 2021 at 09:31:42PM +0200, Alvin Šipraga wrote:
> +/* Table LUT (look-up-table) address register */
> +#define RTL8365MB_TABLE_LUT_ADDR_REG			0x0502
> +#define   RTL8365MB_TABLE_LUT_ADDR_ADDRESS2_MASK	0x4000
> +#define   RTL8365MB_TABLE_LUT_ADDR_BUSY_FLAG_MASK	0x2000
> +#define   RTL8365MB_TABLE_LUT_ADDR_HIT_STATUS_MASK	0x1000
> +#define   RTL8365MB_TABLE_LUT_ADDR_TYPE_MASK		0x0800
> +#define   RTL8365MB_TABLE_LUT_ADDR_ADDRESS_MASK		0x07FF

FDB/MDB operations should be possible.

> +/* Port isolation (forwarding mask) registers */
> +#define RTL8365MB_PORT_ISOLATION_REG_BASE		0x08A2
> +#define RTL8365MB_PORT_ISOLATION_REG(_physport) \
> +		(RTL8365MB_PORT_ISOLATION_REG_BASE + (_physport))
> +#define   RTL8365MB_PORT_ISOLATION_MASK			0x07FF

Bridge offload should be implemented with these isolation registers.



FYI:
https://cdn.jsdelivr.net/gh/libc0607/Realtek_switch_hacking@files/Realtek_Unmanaged_Switch_ProgrammingGuide.pdf