lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite for Android: free password hash cracker in your pocket
[<prev] [next>] [<thread-prev] [day] [month] [year] [list]
Date:   Tue, 31 Aug 2021 00:06:30 +0200
From:   Linus Walleij <linus.walleij@...aro.org>
To:     Vladimir Oltean <olteanv@...il.com>
Cc:     Andrew Lunn <andrew@...n.ch>,
        Vivien Didelot <vivien.didelot@...il.com>,
        Florian Fainelli <f.fainelli@...il.com>,
        "David S . Miller" <davem@...emloft.net>,
        Jakub Kicinski <kuba@...nel.org>,
        netdev <netdev@...r.kernel.org>,
        DENG Qingfang <dqfext@...il.com>,
        Alvin Šipraga <alsi@...g-olufsen.dk>,
        Mauri Sandberg <sandberg@...lfence.com>
Subject: Re: [PATCH net-next 1/2] net: dsa: rtl8366rb: support bridge offloading

On Tue, Aug 31, 2021 at 12:01 AM Vladimir Oltean <olteanv@...il.com> wrote:
> On Mon, Aug 30, 2021 at 11:22:11PM +0200, Linus Walleij wrote:
> > On Mon, Aug 30, 2021 at 10:12 AM Vladimir Oltean <olteanv@...il.com> wrote:
> >
> > > > +/* Port isolation registers */
> > > > +#define RTL8366RB_PORT_ISO_BASE              0x0F08
> > > > +#define RTL8366RB_PORT_ISO(pnum)     (RTL8366RB_PORT_ISO_BASE + (pnum))
> > > > +#define RTL8366RB_PORT_ISO_EN                BIT(0)
> > > > +#define RTL8366RB_PORT_ISO_PORTS_MASK        GENMASK(7, 1)
> > >
> > > If RTL8366RB_NUM_PORTS is 6, then why is RTL8366RB_PORT_ISO_PORTS_MASK a
> > > 7-bit field?
> >
> > It's a 6 bit field actually from bit 1 to bit 7 just shifted up one
> > bit because bit 0 is "enable".
>
> Understood the part about bit 0 being "ENABLE".
> But from bit 1 to bit 7, I count 7 bits set....

Oh yeah.... something is wrong with my arithmetics.

Bit 0: enable
Bit 1: port 0
Bit 2: port 1
Bit 3: port 2
Bit 4: port 3
Bit 5: port 4
Bit 6: port 5 - CPU

I'll fix with the rest of the comments for v3.

Yours,
Linus Walleij

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ