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Message-ID: <CACRpkdb7yhraJNH=b=mv=bE7p6Q_k-Yy0M9YT9QctKC1GLhVEw@mail.gmail.com>
Date: Tue, 7 Sep 2021 19:48:43 +0200
From: Linus Walleij <linus.walleij@...aro.org>
To: Vladimir Oltean <olteanv@...il.com>
Cc: Andrew Lunn <andrew@...n.ch>,
Vivien Didelot <vivien.didelot@...il.com>,
Florian Fainelli <f.fainelli@...il.com>,
"David S . Miller" <davem@...emloft.net>,
Jakub Kicinski <kuba@...nel.org>,
netdev <netdev@...r.kernel.org>,
Alvin Šipraga <alsi@...g-olufsen.dk>,
Mauri Sandberg <sandberg@...lfence.com>,
DENG Qingfang <dqfext@...il.com>
Subject: Re: [PATCH net-next 5/5 v2] net: dsa: rtl8366rb: Support fast aging
On Tue, Aug 31, 2021 at 12:46 AM Vladimir Oltean <olteanv@...il.com> wrote:
> > + /* This will age out any L2 entries */
>
> Clarify "any L2 entries". The fdb flushing process should remove the
> dynamically learned FDB entries, it should keep the static ones. Did you
> say "any" because rtl8366rb does not implement static FDB entries via
> .port_fdb_add, and therefore all entries are dynamic, or does it really
> delete static FDB entries?
It's what Realtek calls "L2 entries" sadly I do not fully understand
their lingo.
The ASIC can do static L2 entries as well, but I haven't looked into
that. The (confused) docs for the function that set these bits is
the following:
"ASIC will age out L2 entry with fields Static, Auth and IP_MULT are 0.
Aging out function is for new address learning LUT update because
size of LUT is limited, old address information should not be kept and
get more new learning SA information. Age field of L2 LUT is updated
by following sequence {0b10,0b11,0b01,0b00} which means the LUT
entries with age value 0b00 is free for ASIC. ASIC will use this aging
sequence to decide which entry to be replace by new SA learning
information. This function can be replace by setting STP state each
port."
Next it sets the bit for the port in register
RTL8366RB_SECURITY_CTRL.
Realtek talks about "LUT" which I think is the same as "FDB"
(which I assume is forwarding database, I'm not good with this stuff).
My interpretation of this convoluted text is that static, auth and ip_mult
will *not* be affected ("are 0"), but only learned entries in the LUT/FDB
will be affected. The sequence listed in the comment I interpret as a
reference to what the ASIC is doing with the age field for the entry
internally to achieve this. Then I guess they say that one can also
do fast aging by stopping the port (duh).
I'll update the doc to say "any learned L2 entries", but eager to hear
what you say about it too :)
Yours,
Linus Walleij
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