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Message-ID: <20210923202231.t2zjoejpxrbbe5hc@pali>
Date: Thu, 23 Sep 2021 22:22:31 +0200
From: Pali Rohár <pali@...nel.org>
To: Andy Shevchenko <andy.shevchenko@...il.com>
Cc: Jonas Dreßler <verdre@...d.nl>,
Brian Norris <briannorris@...omium.org>,
Amitkumar Karwar <amitkarwar@...il.com>,
Ganapathi Bhat <ganapathi017@...il.com>,
Xinming Hu <huxinming820@...il.com>,
Kalle Valo <kvalo@...eaurora.org>,
"David S. Miller" <davem@...emloft.net>,
Jakub Kicinski <kuba@...nel.org>,
Tsuchiya Yuto <kitakar@...il.com>,
linux-wireless <linux-wireless@...r.kernel.org>,
netdev@...r.kernel.org,
Linux Kernel <linux-kernel@...r.kernel.org>,
linux-pci <linux-pci@...r.kernel.org>,
Maximilian Luz <luzmaximilian@...il.com>,
Andy Shevchenko <andriy.shevchenko@...ux.intel.com>,
Bjorn Helgaas <bhelgaas@...gle.com>
Subject: Re: [PATCH 1/2] mwifiex: Use non-posted PCI register writes
On Thursday 23 September 2021 22:41:30 Andy Shevchenko wrote:
> On Thu, Sep 23, 2021 at 6:28 PM Jonas Dreßler <verdre@...d.nl> wrote:
> > On 9/22/21 2:50 PM, Jonas Dreßler wrote:
>
> ...
>
> > - Just calling mwifiex_write_reg() once and then blocking until the card
> > wakes up using my delay-loop doesn't fix the issue, it's actually
> > writing multiple times that fixes the issue
> >
> > These observations sound a lot like writes (and even reads) are actually
> > being dropped, don't they?
>
> It sounds like you're writing into a not ready (fully powered on) device.
This reminds me a discussion with Bjorn about CRS response returned
after firmware crash / reset when device is not ready yet:
https://lore.kernel.org/linux-pci/20210922164803.GA203171@bhelgaas/
Could not be this similar issue? You could check it via reading
PCI_VENDOR_ID register from config space. And if it is not valid value
then card is not really ready yet.
> To check this, try to put a busy loop for reading and check the value
> till it gets 0.
>
> Something like
>
> unsigned int count = 1000;
>
> do {
> if (mwifiex_read_reg(...) == 0)
> break;
> } while (--count);
>
>
> --
> With Best Regards,
> Andy Shevchenko
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