netdev - Re: [PATCH 05/10] ravb: Initialize GbEthernet DMAC

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Message-ID: <fb9d4094-6458-f0b3-9e41-be5903f2800e@gmail.com>
Date:   Mon, 4 Oct 2021 18:50:53 +0300
From:   Sergei Shtylyov <sergei.shtylyov@...il.com>
To:     Biju Das <biju.das.jz@...renesas.com>,
        Sergey Shtylyov <s.shtylyov@....ru>,
        "David S. Miller" <davem@...emloft.net>,
        Jakub Kicinski <kuba@...nel.org>
Cc:     Geert Uytterhoeven <geert+renesas@...der.be>,
        Sergey Shtylyov <s.shtylyov@...russia.ru>,
        Adam Ford <aford173@...il.com>, Andrew Lunn <andrew@...n.ch>,
        Yuusuke Ashizuka <ashiduka@...itsu.com>,
        Yoshihiro Shimoda <yoshihiro.shimoda.uh@...esas.com>,
        "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
        "linux-renesas-soc@...r.kernel.org" 
        <linux-renesas-soc@...r.kernel.org>,
        Chris Paterson <Chris.Paterson2@...esas.com>,
        Biju Das <biju.das@...renesas.com>,
        Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@...renesas.com>
Subject: Re: [PATCH 05/10] ravb: Initialize GbEthernet DMAC

On 10/4/21 4:12 PM, Biju Das wrote:

>> Subject: Re: [PATCH 05/10] ravb: Initialize GbEthernet DMAC
>>
>> Hello!
>>
>> On 10/1/21 6:06 PM, Biju Das wrote:
>>
>>> Initialize GbEthernet DMAC found on RZ/G2L SoC.
>>>
>>> Signed-off-by: Biju Das <biju.das.jz@...renesas.com>
>>> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@...renesas.com>
>>> ---
>>> RFC->v1:
>>>  * Removed RIC3 initialization from DMAC init, as it is
>>>    same as reset value.
>>
>>    I'm not sure we do a reset everytime...
>>
>>>  * moved stubs function to earlier patches.
>>>  * renamed "rgeth" with "gbeth"
>>> ---
>>>  drivers/net/ethernet/renesas/ravb.h      |  3 ++-
>>>  drivers/net/ethernet/renesas/ravb_main.c | 30
>>> +++++++++++++++++++++++-
>>>  2 files changed, 31 insertions(+), 2 deletions(-)
>>>
>> [...]
>>> diff --git a/drivers/net/ethernet/renesas/ravb_main.c
>>> b/drivers/net/ethernet/renesas/ravb_main.c
>>> index dc817b4d95a1..5790a9332e7b 100644
>>> --- a/drivers/net/ethernet/renesas/ravb_main.c
>>> +++ b/drivers/net/ethernet/renesas/ravb_main.c
>>> @@ -489,7 +489,35 @@ static void ravb_emac_init(struct net_device
>>> *ndev)
>>>
>>>  static int ravb_dmac_init_gbeth(struct net_device *ndev)  {
>>> -	/* Place holder */
>>> +	int error;
>>> +
>>> +	error = ravb_ring_init(ndev, RAVB_BE);
>>> +	if (error)
>>> +		return error;
>>> +
>>> +	/* Descriptor format */
>>> +	ravb_ring_format(ndev, RAVB_BE);
>>> +
>>> +	/* Set AVB RX */
>>
>>    AVB? We don't have it, do we?
> 
> Good catch. I Will update the comment in next RFC patch.

   That's trifles, not worth a patch on its own...

>>
>>> +	ravb_write(ndev, 0x60000000, RCR);
>>
>>    Not even RCR.EFFS? And what do bits 29..30 mean?
> 
> RZ/G2L Bit 31 is reserved.
> Bit 16:30 Reception fifo critical level.
> Bit 15:1 reserved
> Bit 0 : EFFS
> 
> I am not sure, where do you get 29..30? can you please clarify.

   0x60000000 has bits 29..30 set and gen3 manual has these bits reserved. 

>> [...]
>>> +	/* Set FIFO size */
>>> +	ravb_write(ndev, 0x00222200, TGC);
>>
>>    Do TBD<n> (other than TBD0) fields even exist?
> 
> Only TBD (Bit 8..9) is available to write,

   Thought so! :-)

> rest all are reserved with remaining values
> as in "0x00222200"

  Oh, so the defaluts are the sme on RZ/G2L, despite only 1 TX queue?

> Regds,
> Biju

MBR, Sergey