netdev - Re: [net-next PATCH v5 04/14] dt-bindings: net: dsa: qca8k: Document support for CPU port 6

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Sun, 10 Oct 2021 18:50:39 -0700
From:   Florian Fainelli <f.fainelli@...il.com>
To:     Ansuel Smith <ansuelsmth@...il.com>, Andrew Lunn <andrew@...n.ch>,
        Vivien Didelot <vivien.didelot@...il.com>,
        Vladimir Oltean <olteanv@...il.com>,
        "David S. Miller" <davem@...emloft.net>,
        Jakub Kicinski <kuba@...nel.org>,
        Rob Herring <robh+dt@...nel.org>,
        Russell King <linux@...linux.org.uk>, netdev@...r.kernel.org,
        devicetree@...r.kernel.org, linux-kernel@...r.kernel.org
Subject: Re: [net-next PATCH v5 04/14] dt-bindings: net: dsa: qca8k: Document
 support for CPU port 6



On 10/10/2021 6:30 PM, Ansuel Smith wrote:
> The switch now support CPU port to be set 6 instead of be hardcoded to
> 0. Document support for it and describe logic selection.
> 
> Signed-off-by: Ansuel Smith <ansuelsmth@...il.com>
> ---
>   Documentation/devicetree/bindings/net/dsa/qca8k.txt | 6 +++++-
>   1 file changed, 5 insertions(+), 1 deletion(-)
> 
> diff --git a/Documentation/devicetree/bindings/net/dsa/qca8k.txt b/Documentation/devicetree/bindings/net/dsa/qca8k.txt
> index cc214e655442..aeb206556f54 100644
> --- a/Documentation/devicetree/bindings/net/dsa/qca8k.txt
> +++ b/Documentation/devicetree/bindings/net/dsa/qca8k.txt
> @@ -29,7 +29,11 @@ the mdio MASTER is used as communication.
>   Don't use mixed external and internal mdio-bus configurations, as this is
>   not supported by the hardware.
>   
> -The CPU port of this switch is always port 0.
> +This switch support 2 CPU port. 

Plural: ports.

> Normally and advised configuration is with
> +CPU port set to port 0. It is also possible to set the CPU port to port 6
> +if the device requires it. The driver will configure the switch to the defined
> +port. With both CPU port declared the first CPU port is selected as primary
> +and the secondary CPU ignored.

Is this universally supported by all models that this binding covers? If 
not, you might want to explain that?
-- 
Florian