netdev - [PATCH net-next] mlx5: prevent 64bit divide

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Message-Id: <20211018172608.1069754-1-kuba@kernel.org>
Date:   Mon, 18 Oct 2021 10:26:08 -0700
From:   Jakub Kicinski <kuba@...nel.org>
To:     davem@...emloft.net
Cc:     netdev@...r.kernel.org, saeedm@...dia.com, amirtz@...dia.com,
        Jakub Kicinski <kuba@...nel.org>
Subject: [PATCH net-next] mlx5: prevent 64bit divide

mlx5_tout_ms() returns a u64, we can't directly divide it.
This is not a problem here, @timeout which is the value
that actually matters here is already a ulong, so this
implies storing return value of mlx5_tout_ms() on a ulong
should be fine.

This fixes:

  ERROR: modpost: "__udivdi3" [drivers/net/ethernet/mellanox/mlx5/core/mlx5_core.ko] undefined!

Fixes: 32def4120e48 ("net/mlx5: Read timeout values from DTOR")
Signed-off-by: Jakub Kicinski <kuba@...nel.org>
---
 drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c b/drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c
index eaca79cc7b9d..0b0234f9d694 100644
--- a/drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c
+++ b/drivers/net/ethernet/mellanox/mlx5/core/fw_reset.c
@@ -396,13 +396,14 @@ static int fw_reset_event_notifier(struct notifier_block *nb, unsigned long acti
 
 int mlx5_fw_reset_wait_reset_done(struct mlx5_core_dev *dev)
 {
-	unsigned long timeout = msecs_to_jiffies(mlx5_tout_ms(dev, PCI_SYNC_UPDATE));
+	unsigned long pci_sync_update_timeout = mlx5_tout_ms(dev, PCI_SYNC_UPDATE);
+	unsigned long timeout = msecs_to_jiffies(pci_sync_update_timeout);
 	struct mlx5_fw_reset *fw_reset = dev->priv.fw_reset;
 	int err;
 
 	if (!wait_for_completion_timeout(&fw_reset->done, timeout)) {
-		mlx5_core_warn(dev, "FW sync reset timeout after %llu seconds\n",
-			       mlx5_tout_ms(dev, PCI_SYNC_UPDATE) / 1000);
+		mlx5_core_warn(dev, "FW sync reset timeout after %lu seconds\n",
+			       pci_sync_update_timeout / 1000);
 		err = -ETIMEDOUT;
 		goto out;
 	}
-- 
2.31.1