netdev - Re: [PATCH V11 7/8] PCI: Enable 10-Bit Tag support for PCIe Endpoint device

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Date:   Mon, 1 Nov 2021 17:02:39 -0500
From:   Bjorn Helgaas <helgaas@...nel.org>
To:     Dongdong Liu <liudongdong3@...wei.com>
Cc:     hch@...radead.org, kw@...ux.com, logang@...tatee.com,
        leon@...nel.org, linux-pci@...r.kernel.org, rajur@...lsio.com,
        hverkuil-cisco@...all.nl, linux-media@...r.kernel.org,
        netdev@...r.kernel.org
Subject: Re: [PATCH V11 7/8] PCI: Enable 10-Bit Tag support for PCIe Endpoint
 device

On Sat, Oct 30, 2021 at 09:53:47PM +0800, Dongdong Liu wrote:
> 10-Bit Tag capability, introduced in PCIe-4.0 increases the total Tag
> field size from 8 bits to 10 bits.
> 
> PCIe spec 5.0 r1.0 section 2.2.6.2 "Considerations for Implementing
> 10-Bit Tag Capabilities" Implementation Note:
> 
>   For platforms where the RC supports 10-Bit Tag Completer capability,
>   it is highly recommended for platform firmware or operating software
>   that configures PCIe hierarchies to Set the 10-Bit Tag Requester Enable
>   bit automatically in Endpoints with 10-Bit Tag Requester capability.
>   This enables the important class of 10-Bit Tag capable adapters that
>   send Memory Read Requests only to host memory.
> 
> It's safe to enable 10-bit tags for all devices below a Root Port that
> supports them. Switches that lack 10-Bit Tag Completer capability are
> still able to forward NPRs and Completions carrying 10-Bit Tags correctly,
> since the two new Tag bits are in TLP Header bits that were formerly
> Reserved.

Side note: the reason we want to do this to increase performance by
allowing more outstanding requests.  Do you have any benchmarking that
we can mention here to show that this is actually a benefit?  I don't
doubt that it is, but I assume you've measured it and it would be nice
to advertise it.

Bjorn