netdev - [PATCH RFC net-next 3/3] net: ag71xx: convert to phylink_get

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [day] [month] [year] [list]

Message-Id: <E1mnMsM-007y7z-F5@rmk-PC.armlinux.org.uk>
Date:   Wed, 17 Nov 2021 15:29:30 +0000
From:   "Russell King (Oracle)" <rmk+kernel@...linux.org.uk>
To:     Chris Snook <chris.snook@...il.com>,
        Oleksij Rempel <linux@...pel-privat.de>
Cc:     netdev@...r.kernel.org
Subject: [PATCH RFC net-next 3/3] net: ag71xx: convert to
 phylink_get_linkmodes()

ag71xx only supports MII port type, so can't use the generic phylink
validation callback. Update to use phylink_get_linkmodes() instead.

Signed-off-by: Russell King (Oracle) <rmk+kernel@...linux.org.uk>
---
This implementation seems wrong. If it only supports the MII port type,
then it doesn't support fibre or twisted pair - yet it can as a PHY can
be connected. If this can be fixed, we can convert it to use
phylink_generic_validate() and get rid of ag71xx_mac_validate()
entirely.

 drivers/net/ethernet/atheros/ag71xx.c | 16 +++-------------
 1 file changed, 3 insertions(+), 13 deletions(-)

diff --git a/drivers/net/ethernet/atheros/ag71xx.c b/drivers/net/ethernet/atheros/ag71xx.c
index 20c2cfdc30da..2d2725b2a6ae 100644
--- a/drivers/net/ethernet/atheros/ag71xx.c
+++ b/drivers/net/ethernet/atheros/ag71xx.c
@@ -1032,20 +1032,8 @@ static void ag71xx_mac_validate(struct phylink_config *config,
 
 	phylink_set(mask, MII);
 
-	phylink_set(mask, Pause);
-	phylink_set(mask, Asym_Pause);
 	phylink_set(mask, Autoneg);
-	phylink_set(mask, 10baseT_Half);
-	phylink_set(mask, 10baseT_Full);
-	phylink_set(mask, 100baseT_Half);
-	phylink_set(mask, 100baseT_Full);
-
-	if (state->interface == PHY_INTERFACE_MODE_SGMII ||
-	    state->interface == PHY_INTERFACE_MODE_RGMII ||
-	    state->interface == PHY_INTERFACE_MODE_GMII) {
-		phylink_set(mask, 1000baseT_Full);
-		phylink_set(mask, 1000baseX_Full);
-	}
+	phylink_get_linkmodes(mask, state->interface, config->mac_capabilities);
 
 	linkmode_and(supported, supported, mask);
 	linkmode_and(state->advertising, state->advertising, mask);
@@ -1138,6 +1126,8 @@ static int ag71xx_phylink_setup(struct ag71xx *ag)
 
 	ag->phylink_config.dev = &ag->ndev->dev;
 	ag->phylink_config.type = PHYLINK_NETDEV;
+	ag->phylink_config.mac_capabilities = MAC_SYM_PAUSE | MAC_ASYM_PAUSE |
+		MAC_10 | MAC_100 | MAC_1000FD;
 
 	if ((ag71xx_is(ag, AR9330) && ag->mac_idx == 0) ||
 	    ag71xx_is(ag, AR9340) ||
-- 
2.30.2