netdev - [PATCH net 6/9] can: m_can: pci: fix incorrect reference clock rate

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Message-Id: <20211207102420.120131-7-mkl@pengutronix.de>
Date:   Tue,  7 Dec 2021 11:24:17 +0100
From:   Marc Kleine-Budde <mkl@...gutronix.de>
To:     netdev@...r.kernel.org
Cc:     davem@...emloft.net, kuba@...nel.org, linux-can@...r.kernel.org,
        kernel@...gutronix.de,
        Matthias Schiffer <matthias.schiffer@...tq-group.com>,
        stable@...r.kernel.org,
        Jarkko Nikula <jarkko.nikula@...ux.intel.com>,
        Marc Kleine-Budde <mkl@...gutronix.de>
Subject: [PATCH net 6/9] can: m_can: pci: fix incorrect reference clock rate

From: Matthias Schiffer <matthias.schiffer@...tq-group.com>

When testing the CAN controller on our Ekhart Lake hardware, we
determined that all communication was running with twice the configured
bitrate. Changing the reference clock rate from 100MHz to 200MHz fixed
this. Intel's support has confirmed to us that 200MHz is indeed the
correct clock rate.

Fixes: cab7ffc0324f ("can: m_can: add PCI glue driver for Intel Elkhart Lake")
Link: https://lore.kernel.org/all/c9cf3995f45c363e432b3ae8eb1275e54f009fc8.1636967198.git.matthias.schiffer@ew.tq-group.com
Cc: stable@...r.kernel.org
Signed-off-by: Matthias Schiffer <matthias.schiffer@...tq-group.com>
Acked-by: Jarkko Nikula <jarkko.nikula@...ux.intel.com>
Reviewed-by: Jarkko Nikula <jarkko.nikula@...ux.intel.com>
Signed-off-by: Marc Kleine-Budde <mkl@...gutronix.de>
---
 drivers/net/can/m_can/m_can_pci.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/can/m_can/m_can_pci.c b/drivers/net/can/m_can/m_can_pci.c
index d72c294ac4d3..8f184a852a0a 100644
--- a/drivers/net/can/m_can/m_can_pci.c
+++ b/drivers/net/can/m_can/m_can_pci.c
@@ -18,7 +18,7 @@
 
 #define M_CAN_PCI_MMIO_BAR		0
 
-#define M_CAN_CLOCK_FREQ_EHL		100000000
+#define M_CAN_CLOCK_FREQ_EHL		200000000
 #define CTL_CSR_INT_CTL_OFFSET		0x508
 
 struct m_can_pci_priv {
-- 
2.33.0