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Message-Id: <20220103183556.41040-2-hch@lst.de> Date: Mon, 3 Jan 2022 19:35:51 +0100 From: Christoph Hellwig <hch@....de> To: Jonathan Corbet <corbet@....net>, Alexei Starovoitov <ast@...nel.org>, Daniel Borkmann <daniel@...earbox.net>, Andrii Nakryiko <andrii@...nel.org> Cc: Martin KaFai Lau <kafai@...com>, Song Liu <songliubraving@...com>, Yonghong Song <yhs@...com>, John Fastabend <john.fastabend@...il.com>, KP Singh <kpsingh@...nel.org>, linux-doc@...r.kernel.org, netdev@...r.kernel.org, bpf@...r.kernel.org Subject: [PATCH 1/6] bpf, docs: Add a setion to explain the basic instruction encoding The eBPF instruction set document does not currently document the basic instruction encoding. Add a section to do that. Signed-off-by: Christoph Hellwig <hch@....de> --- Documentation/bpf/instruction-set.rst | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/Documentation/bpf/instruction-set.rst b/Documentation/bpf/instruction-set.rst index 1af51143ff9f6..80f42984b5942 100644 --- a/Documentation/bpf/instruction-set.rst +++ b/Documentation/bpf/instruction-set.rst @@ -19,8 +19,22 @@ The eBPF calling convention is defined as: R0 - R5 are scratch registers and eBPF programs needs to spill/fill them if necessary across calls. +Instruction encoding +==================== + +eBPF uses 64-bit instructions with the following encoding: + + ============= ======= =============== ==================== ============ + 32 bits (MSB) 16 bits 4 bits 4 bits 8 bits (LSB) + ============= ======= =============== ==================== ============ + immediate offset source register destination register opcode + ============= ======= =============== ==================== ============ + +Note that most instructions do not use all of the fields. +Unused fields shall be cleared to zero. + Instruction classes -=================== +------------------- The three LSB bits of the 'opcode' field store the instruction class: -- 2.30.2
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