netdev - [PATCH net 0/7] Xilinx axienet fixes

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Message-Id: <20220111211358.2699350-1-robert.hancock@calian.com>
Date:   Tue, 11 Jan 2022 15:13:51 -0600
From:   Robert Hancock <robert.hancock@...ian.com>
To:     netdev@...r.kernel.org
Cc:     radhey.shyam.pandey@...inx.com, davem@...emloft.net,
        kuba@...nel.org, Robert Hancock <robert.hancock@...ian.com>
Subject: [PATCH net 0/7] Xilinx axienet fixes

Various fixes for the Xilinx AXI Ethernet driver.

Robert Hancock (7):
  net: axienet: Reset core before accessing MAC and wait for core ready
  net: axienet: add missing memory barriers
  net: axienet: limit minimum TX ring size
  net: axienet: Fix TX ring slot available check
  net: axienet: fix number of TX ring slots for available check
  net: axienet: fix for TX busy handling
  net: axienet: increase default TX ring size to 128

 .../net/ethernet/xilinx/xilinx_axienet_main.c | 134 +++++++++++-------
 1 file changed, 83 insertions(+), 51 deletions(-)

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2.31.1