netdev - Re: [PATCH net v2 3/9] net: axienet: reset core on initialization prior to MDIO access

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Date:   Wed, 12 Jan 2022 20:21:35 +0100
From:   Andrew Lunn <andrew@...n.ch>
To:     Robert Hancock <robert.hancock@...ian.com>
Cc:     netdev@...r.kernel.org, radhey.shyam.pandey@...inx.com,
        davem@...emloft.net, kuba@...nel.org,
        linux-arm-kernel@...ts.infradead.org, michal.simek@...inx.com,
        ariane.keller@....ee.ethz.ch, daniel@...earbox.net
Subject: Re: [PATCH net v2 3/9] net: axienet: reset core on initialization
 prior to MDIO access

On Wed, Jan 12, 2022 at 11:36:54AM -0600, Robert Hancock wrote:
> In some cases where the Xilinx Ethernet core was used in 1000Base-X or
> SGMII modes, which use the internal PCS/PMA PHY, and the MGT
> transceiver clock source for the PCS was not running at the time the
> FPGA logic was loaded, the core would come up in a state where the
> PCS could not be found on the MDIO bus. To fix this, the Ethernet core
> (including the PCS) should be reset after enabling the clocks, prior to
> attempting to access the PCS using of_mdio_find_device.
> 
> Fixes: 1a02556086fc (net: axienet: Properly handle PCS/PMA PHY for 1000BaseX mode)
> Signed-off-by: Robert Hancock <robert.hancock@...ian.com>

Reviewed-by: Andrew Lunn <andrew@...n.ch>

    Andrew