netdev - Re: [PATCH net v2 2/9] net: axienet: Wait for PhyRstCmplt after core reset

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Date:   Wed, 12 Jan 2022 20:44:58 +0100
From:   Andrew Lunn <andrew@...n.ch>
To:     Robert Hancock <robert.hancock@...ian.com>
Cc:     "daniel@...earbox.net" <daniel@...earbox.net>,
        "radhey.shyam.pandey@...inx.com" <radhey.shyam.pandey@...inx.com>,
        "michal.simek@...inx.com" <michal.simek@...inx.com>,
        "kuba@...nel.org" <kuba@...nel.org>,
        "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
        "davem@...emloft.net" <davem@...emloft.net>,
        "ariane.keller@....ee.ethz.ch" <ariane.keller@....ee.ethz.ch>
Subject: Re: [PATCH net v2 2/9] net: axienet: Wait for PhyRstCmplt after core
 reset

> > Is this bit guaranteed to be clear before you start waiting for it?
> 
> The documentation for the IP core ( 
> https://www.xilinx.com/content/dam/xilinx/support/documentation/ip_documentation/axi_ethernet/v7_2/pg138-axi-ethernet.pdf
>  ) states for the phy_rst_n output signal: "This active-Low reset is held
> active for 10 ms after power is applied and during any reset. After the reset
> goes inactive, the PHY cannot be accessed for an additional 5 ms." The
> PhyRstComplt bit definition mentions "This signal does not transition to 1 for
> 5 ms after PHY_RST_N transitions to 1". Given that a reset of the core has just
> been completed above, the PHY reset should at least have been initiated as
> well, so it should be sufficient to just wait for the bit to become 1 at this
> point.

Great, thanks for checking.

Reviewed-by: Andrew Lunn <andrew@...n.ch>

    Andrew