netdev - RE: [PATCH net v3 0/9] Xilinx axienet fixes

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Message-ID: <SA1PR02MB85601DA6A4009BA3FDAF256BC7599@SA1PR02MB8560.namprd02.prod.outlook.com>
Date:   Wed, 19 Jan 2022 07:07:37 +0000
From:   Radhey Shyam Pandey <radheys@...inx.com>
To:     Robert Hancock <robert.hancock@...ian.com>,
        "netdev@...r.kernel.org" <netdev@...r.kernel.org>
CC:     "linux-arm-kernel@...ts.infradead.org" 
        <linux-arm-kernel@...ts.infradead.org>,
        "davem@...emloft.net" <davem@...emloft.net>,
        "kuba@...nel.org" <kuba@...nel.org>,
        Michal Simek <michals@...inx.com>,
        "daniel@...earbox.net" <daniel@...earbox.net>,
        "andrew@...n.ch" <andrew@...n.ch>,
        Harini Katakam <harinik@...inx.com>
Subject: RE: [PATCH net v3 0/9] Xilinx axienet fixes

> -----Original Message-----
> From: Robert Hancock <robert.hancock@...ian.com>
> Sent: Wednesday, January 19, 2022 4:35 AM
> To: netdev@...r.kernel.org
> Cc: linux-arm-kernel@...ts.infradead.org; davem@...emloft.net;
> kuba@...nel.org; Michal Simek <michals@...inx.com>; Radhey Shyam Pandey
> <radheys@...inx.com>; daniel@...earbox.net; andrew@...n.ch
> Subject: Re: [PATCH net v3 0/9] Xilinx axienet fixes
> 
> On Tue, 2022-01-18 at 15:41 -0600, Robert Hancock wrote:
> > Various fixes for the Xilinx AXI Ethernet driver.
> >
> > Changed since v2:
> > -added Reviewed-by tags, added some explanation to commit messages, no
> > code changes
> >
> > Changed since v1:
> > -corrected a Fixes tag to point to mainline commit -split up reset
> > changes into 3 patches -added ratelimit on netdev_warn in TX busy case
> >
> > Robert Hancock (9):
> >   net: axienet: increase reset timeout
> >   net: axienet: Wait for PhyRstCmplt after core reset
> >   net: axienet: reset core on initialization prior to MDIO access
> >   net: axienet: add missing memory barriers
> >   net: axienet: limit minimum TX ring size
> >   net: axienet: Fix TX ring slot available check
> >   net: axienet: fix number of TX ring slots for available check
> >   net: axienet: fix for TX busy handling
> >   net: axienet: increase default TX ring size to 128
> >
> >  .../net/ethernet/xilinx/xilinx_axienet_main.c | 135
> > +++++++++++-------
> >  1 file changed, 84 insertions(+), 51 deletions(-)
> >
> 
> FYI, for the netdev/cc_maintainers Patchwork check, I dropped Ariane Keller <
> ariane.keller@....ee.ethz.ch> from the CC list as their mail was bouncing.

Thanks for the series. I have added Harini to this thread to also review
and add her Tested-by tag. Just FYI- We are in feature freeze so plan is
to close on this series by next week. Hope that's fine.

> 
> --
> Robert Hancock
> Senior Hardware Designer, Calian Advanced Technologies www.calian.com