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Message-ID: <be8e3fba-a76c-9bb1-39ee-d6069f234c93@arinc9.com>
Date: Fri, 21 Jan 2022 12:07:08 +0300
From: Arınç ÜNAL <arinc.unal@...nc9.com>
To: Florian Fainelli <f.fainelli@...il.com>,
Luiz Angelo Daros de Luca <luizluca@...il.com>
Cc: Vladimir Oltean <olteanv@...il.com>, Andrew Lunn <andrew@...n.ch>,
Frank Wunderlich <frank-w@...lic-files.de>,
Alvin Šipraga <ALSI@...g-olufsen.dk>,
"netdev@...r.kernel.org" <netdev@...r.kernel.org>,
"linus.walleij@...aro.org" <linus.walleij@...aro.org>,
"vivien.didelot@...il.com" <vivien.didelot@...il.com>,
erkin.bozoglu@...ont.com,
Sergio Paracuellos <sergio.paracuellos@...il.com>,
gregkh@...uxfoundation.org
Subject: Re: [PATCH net-next v4 11/11] net: dsa: realtek: rtl8365mb: multiple
cpu ports, non cpu extint
On 21/01/2022 06:50, Florian Fainelli wrote:
>
>
> On 1/20/2022 7:42 PM, Luiz Angelo Daros de Luca wrote:
>>> Are we talking about an in tree driver? If so which is it?
>>
>> Yes, the one the patch touches: rtl8365mb.
>
> I meant the DSA master network device, but you answered that, it uses a
> mt7260a SoC, but there is no Ethernet driver upstream for it yet?
>
> git grep ralink,mt7620-gsw *
> Documentation/devicetree/bindings/net/mediatek,mt7620-gsw.txt:
> compatible = "ralink,mt7620-gsw";
>
>>
>> My device uses a mt7620a SoC and traffic passes through its mt7530
>> switch with vlan disabled before reaching the realtek switch. It still
>> loads a swconfig driver but I think it might work without one.
>
> Ah so you have a cascade of switches here, that could confuse your
> Ethernet MAC. Do you have a knob to adjust where to calculate the
> checksum from, say a L2 or L3 offset for instance?
The company I currently work for has got their own mt7621a board with an
external rtl8367s switch.
According to Documentation/devicetree/bindings/net/dsa/mt7530.txt I can
either connect the rtl switch directly to the second GMAC of the mt7621
SoC or to MT7530's GMAC5 to create a cascade.
I've been running gregkh/staging staging-next branch but I can't seem to
have traffic flow on the RGMII2 bus which is shared by the 2nd GMAC of
the SoC, MT7530's GMAC5 and an external phy (rtl switch in this case).
None of the documented configurations work:
PHY0/4 <-> 2nd GMAC
External phy <-> 2nd GMAC
External phy <-> MT7530's GMAC5
Arınç
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