netdev - MT7621 SoC Traffic Won't Flow on RGMII2 Bus/2nd GMAC

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Message-ID: <83a35aa3-6cb8-2bc4-2ff4-64278bbcd8c8@arinc9.com>
Date:   Sat, 22 Jan 2022 21:01:31 +0300
From:   Arınç ÜNAL <arinc.unal@...nc9.com>
To:     Luiz Angelo Daros de Luca <luizluca@...il.com>,
        DENG Qingfang <dqfext@...il.com>,
        Matthias Brugger <matthias.bgg@...il.com>,
        John Crispin <john@...ozen.org>,
        Siddhant Gupta <siddhantgupta416@...il.com>,
        Ilya Lipnitskiy <ilya.lipnitskiy@...il.com>,
        Sergio Paracuellos <sergio.paracuellos@...il.com>,
        Felix Fietkau <nbd@....name>,
        Sean Wang <sean.wang@...iatek.com>,
        Mark Lee <Mark-MC.Lee@...iatek.com>,
        Russell King <linux@...linux.org.uk>,
        Jakub Kicinski <kuba@...nel.org>,
        David Miller <davem@...emloft.net>,
        René van Dorst <opensource@...rst.com>
Cc:     linux-mediatek@...ts.infradead.org, netdev@...r.kernel.org,
        linux-mips@...r.kernel.org, devicetree@...r.kernel.org,
        openwrt-devel@...ts.openwrt.org, erkin.bozoglu@...ont.com
Subject: MT7621 SoC Traffic Won't Flow on RGMII2 Bus/2nd GMAC

Hi all,

The company I currently work for has got an Ralink mt7621a board with an 
external phy connected. It's a Realtek rtl8367s switch.
I've been running gregkh/staging staging-next & netdev/net-next master 
branches with Sergio's "clk: ralink: make system controller a reset 
provider" v8 patch series.

We don't have traffic flow on the RGMII2 bus which is shared by the 2nd 
GMAC of the SoC, MT7530's GMAC5 and an external phy (rtl switch in our 
case).

According to Documentation/devicetree/bindings/net/dsa/mt7530.txt, I can 
either configure the external phy to connect to the second GMAC of the 
mt7621 SoC or to MT7530's GMAC5 to create a cascade.

None of the documented configurations work:
External phy <-> 2nd GMAC
External phy <-> MT7530's GMAC5

The external switch works with Mediatek SDK ethernet driver on External 
phy <-> 2nd GMAC mode.

I suspect there is a problem with the mtk_eth_soc driver on upstream.
Same issue on 5.10 (OpenWrt Master) and 4.14 (OpenWrt 19.07)

The board's RTL8367S schematics is in the attachments.

Dumbed down wiring scheme:
                             CPU
                      ┌───────────────┐
                      │ GMAC0 | GMAC1 │
                      └───┼───────┼───┘
                          │       │
             ┌────────────┼┐      │
      MT7530 │0 1 2 3 4 5 6│      │
             └─────────────┘      │
                          ┌───────┘
             ┌────────────┼┐
    RTL8367S │0 1 2 3 4 6 7│
             └┼─┼─┼─┼─┼────┘
      ┌───────┘ │ │ │ └───────┐
      │     ┌───┘ │ └───┐     │
      │     │     │     │     │
      │     │     │     │     │
  ┌───┼─────┼─────┼─────┼─────┼───┐
  │ sw1p0 sw1p1 sw1p2 sw1p3 sw1p4 │
  └───────────────────────────────┘

Cheers.
Arınç
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