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Message-ID: <660659d112434614b5b4c0dd0aeecf40@realtek.com>
Date: Wed, 26 Jan 2022 11:45:43 +0000
From: Hau <hau@...ltek.com>
To: Heiner Kallweit <hkallweit1@...il.com>,
"netdev@...r.kernel.org" <netdev@...r.kernel.org>
CC: nic_swsd <nic_swsd@...ltek.com>,
"linux-kernel@...r.kernel.org" <linux-kernel@...r.kernel.org>
Subject: RE: [PATCH net-next 1/1] r8169: enable RTL8125 ASPM L1.2
> On 26.01.2022 10:02, Hau wrote:
> >
> >
> >> On 24.01.2022 19:19, Chunhao Lin wrote:
> >>> This patch will enable RTL8125 ASPM L1.2 on the platforms that have
> >>> tested RTL8125 with ASPM L1.2 enabled.
> >>> Register mac ocp 0xc0b2 will help to identify if RTL8125 has been
> >>> tested on L1.2 enabled platform. If it is, this register will be set to 0xf.
> >>> If not, this register will be default value 0.
> >>>
> >>> Signed-off-by: Chunhao Lin <hau@...ltek.com>
> >>> ---
> >>> drivers/net/ethernet/realtek/r8169_main.c | 99
> >>> ++++++++++++++++++-----
> >>> 1 file changed, 79 insertions(+), 20 deletions(-)
> >>>
> >>> diff --git a/drivers/net/ethernet/realtek/r8169_main.c
> >>> b/drivers/net/ethernet/realtek/r8169_main.c
> >>> index 19e2621e0645..b1e013969d4c 100644
> >>> --- a/drivers/net/ethernet/realtek/r8169_main.c
> >>> +++ b/drivers/net/ethernet/realtek/r8169_main.c
> >>> @@ -2238,21 +2238,6 @@ static void rtl_wol_enable_rx(struct
> >> rtl8169_private *tp)
> >>> AcceptBroadcast | AcceptMulticast |
> >> AcceptMyPhys); }
> >>>
> >>> -static void rtl_prepare_power_down(struct rtl8169_private *tp) -{
> >>> - if (tp->dash_type != RTL_DASH_NONE)
> >>> - return;
> >>> -
> >>> - if (tp->mac_version == RTL_GIGA_MAC_VER_32 ||
> >>> - tp->mac_version == RTL_GIGA_MAC_VER_33)
> >>> - rtl_ephy_write(tp, 0x19, 0xff64);
> >>> -
> >>> - if (device_may_wakeup(tp_to_dev(tp))) {
> >>> - phy_speed_down(tp->phydev, false);
> >>> - rtl_wol_enable_rx(tp);
> >>> - }
> >>> -}
> >>> -
> >>> static void rtl_init_rxcfg(struct rtl8169_private *tp) {
> >>> switch (tp->mac_version) {
> >>> @@ -2650,6 +2635,34 @@ static void
> >>> rtl_pcie_state_l2l3_disable(struct
> >> rtl8169_private *tp)
> >>> RTL_W8(tp, Config3, RTL_R8(tp, Config3) & ~Rdy_to_L23); }
> >>>
> >>> +static void rtl_disable_exit_l1(struct rtl8169_private *tp) {
> >>> + /* Bits control which events trigger ASPM L1 exit:
> >>> + * Bit 12: rxdv
> >>> + * Bit 11: ltr_msg
> >>> + * Bit 10: txdma_poll
> >>> + * Bit 9: xadm
> >>> + * Bit 8: pktavi
> >>> + * Bit 7: txpla
> >>> + */
> >>> + switch (tp->mac_version) {
> >>> + case RTL_GIGA_MAC_VER_34 ... RTL_GIGA_MAC_VER_36:
> >>> + rtl_eri_clear_bits(tp, 0xd4, 0x1f00);
> >>> + break;
> >>> + case RTL_GIGA_MAC_VER_37 ... RTL_GIGA_MAC_VER_38:
> >>> + rtl_eri_clear_bits(tp, 0xd4, 0x0c00);
> >>> + break;
> >>> + case RTL_GIGA_MAC_VER_40 ... RTL_GIGA_MAC_VER_53:
> >>> + rtl_eri_clear_bits(tp, 0xd4, 0x1f80);
> >>> + break;
> >>> + case RTL_GIGA_MAC_VER_60 ... RTL_GIGA_MAC_VER_63:
> >>> + r8168_mac_ocp_modify(tp, 0xc0ac, 0x1f80, 0);
> >>> + break;
> >>> + default:
> >>> + break;
> >>> + }
> >>> +}
> >>> +
> >>> static void rtl_enable_exit_l1(struct rtl8169_private *tp) {
> >>> /* Bits control which events trigger ASPM L1 exit:
> >>> @@ -2692,6 +2705,33 @@ static void rtl_hw_aspm_clkreq_enable(struct
> >> rtl8169_private *tp, bool enable)
> >>> udelay(10);
> >>> }
> >>>
> >>> +static void rtl_hw_aspm_l12_enable(struct rtl8169_private *tp, bool
> >>> +enable) {
> >>> + /* Don't enable L1.2 in the chip if OS can't control ASPM */
> >>> + if (enable && tp->aspm_manageable) {
> >>> + r8168_mac_ocp_modify(tp, 0xe094, 0xff00, 0);
> >>> + r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, BIT(2));
> >>> + } else {
> >>> + r8168_mac_ocp_modify(tp, 0xe092, 0x00ff, 0);
> >>> + }
> >>> +}
> >>> +
> >>
> >> Register E094 bits 0..15 are cleared when enabling, but not touched
> >> on disabling. I this correct?
> > Register E094 bits 8...15 is a timer counter that is used to control when to
> disable ephy tx/rx.
> > Set it to 0 means disable ephy tx/rx immediately when certain condition
> meet.
> > It has no meaning when register E092 bit 2 is set to 0.
> >
> Thanks for the explanation.
>
> >> And for basically the same purpose we have the following function.
> >> "don't enable L1.2 in the chip" is not covered by ASPM_en in Config5?
> > Register E092 is like ASPM_en in Config5. But it controls L1 substate
> (L1.1/L1.2) enable status.
> >
> How is this handled for the RTL8168 chip versions supporting L1 sub-states
> (RTL8168h)?
> Is there a similar register or does Config5 ASPM_en control also the L1
> substates on these chip versions?
>
You could apply the same setting on RTL8168H.
> >>
> >> static void rtl_hw_aspm_clkreq_enable(struct rtl8169_private *tp,
> >> bool
> >> enable) {
> >> /* Don't enable ASPM in the chip if OS can't control ASPM */
> >> if (enable && tp->aspm_manageable) {
> >> RTL_W8(tp, Config5, RTL_R8(tp, Config5) | ASPM_en);
> >> RTL_W8(tp, Config2, RTL_R8(tp, Config2) | ClkReqEn);
> >> } else {
> >> RTL_W8(tp, Config2, RTL_R8(tp, Config2) & ~ClkReqEn);
> >> RTL_W8(tp, Config5, RTL_R8(tp, Config5) & ~ASPM_en);
> >> }
> >>
> >> udelay(10);
> >> }
> >>
> >>
> ...
> ------Please consider the environment before printing this e-mail.
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