lists.openwall.net   lists  /  announce  owl-users  owl-dev  john-users  john-dev  passwdqc-users  yescrypt  popa3d-users  /  oss-security  kernel-hardening  musl  sabotage  tlsify  passwords  /  crypt-dev  xvendor  /  Bugtraq  Full-Disclosure  linux-kernel  linux-netdev  linux-ext4  linux-hardening  linux-cve-announce  PHC 
Open Source and information security mailing list archives
 
Hash Suite: Windows password security audit tool. GUI, reports in PDF.
[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]
Message-ID: <YfHe+WAOQDu3hkG1@lunn.ch>
Date:   Thu, 27 Jan 2022 00:53:29 +0100
From:   Andrew Lunn <andrew@...n.ch>
To:     Tobias Waldekranz <tobias@...dekranz.com>
Cc:     davem@...emloft.net, kuba@...nel.org, netdev@...r.kernel.org,
        Vivien Didelot <vivien.didelot@...il.com>,
        Florian Fainelli <f.fainelli@...il.com>,
        Vladimir Oltean <olteanv@...il.com>,
        linux-kernel@...r.kernel.org
Subject: Re: [PATCH net-next 2/2] net: dsa: mv88e6xxx: Improve indirect
 addressing performance

On Thu, Jan 27, 2022 at 12:12:39AM +0100, Tobias Waldekranz wrote:
> Before this change, both the read and write callback would start out
> by asserting that the chip's busy flag was cleared. However, both
> callbacks also made sure to wait for the clearing of the busy bit
> before returning - making the initial check superfluous. The only
> time that would ever have an effect was if the busy bit was initially
> set for some reason.
> 
> With that in mind, make sure to perform an initial check of the busy
> bit, after which both read and write can rely the previous operation
> to have waited for the bit to clear.
> 
> This cuts the number of operations on the underlying MDIO bus by 25%
> 
> Signed-off-by: Tobias Waldekranz <tobias@...dekranz.com>

Reviewed-by: Andrew Lunn <andrew@...n.ch>

    Andrew

Powered by blists - more mailing lists

Powered by Openwall GNU/*/Linux Powered by OpenVZ