| lists.openwall.net | lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC | |
|
Open Source and information security mailing list archives
| ||
|
Message-ID: <20220127173055.308918-5-Raju.Lakkaraju@microchip.com>
Date: Thu, 27 Jan 2022 23:00:54 +0530
From: Raju Lakkaraju <Raju.Lakkaraju@...rochip.com>
To: <netdev@...r.kernel.org>
CC: <davem@...emloft.net>, <kuba@...nel.org>,
<UNGLinuxDriver@...rochip.com>
Subject: [PATCH net-next 4/5] net: lan743x: Add support of selection between SGMII and GMII Interface
PCI1A011/PCI1A041 chip suuport SGMII interface
Signed-off-by: Raju Lakkaraju <Raju.Lakkaraju@...rochip.com>
---
drivers/net/ethernet/microchip/lan743x_main.c | 39 +++++++++++++++++++
drivers/net/ethernet/microchip/lan743x_main.h | 15 +++++++
2 files changed, 54 insertions(+)
diff --git a/drivers/net/ethernet/microchip/lan743x_main.c b/drivers/net/ethernet/microchip/lan743x_main.c
index daba17b0ad6c..6f6655eb6438 100644
--- a/drivers/net/ethernet/microchip/lan743x_main.c
+++ b/drivers/net/ethernet/microchip/lan743x_main.c
@@ -2801,6 +2801,8 @@ static int lan743x_hardware_init(struct lan743x_adapter *adapter,
static int lan743x_mdiobus_init(struct lan743x_adapter *adapter)
{
+ u32 sgmii_ctl;
+ u32 chip_ver;
int ret;
adapter->mdiobus = devm_mdiobus_alloc(&adapter->pdev->dev);
@@ -2809,6 +2811,43 @@ static int lan743x_mdiobus_init(struct lan743x_adapter *adapter)
goto return_error;
}
+ /* GPY211 Interface enable */
+ chip_ver = lan743x_csr_read(adapter, FPGA_REV);
+ if (chip_ver) {
+ netif_info(adapter, drv, adapter->netdev,
+ "FPGA Image version: 0x%08X\n", chip_ver);
+ if (chip_ver & FPGA_SGMII_OP) {
+ sgmii_ctl = lan743x_csr_read(adapter, SGMII_CTL);
+ sgmii_ctl |= SGMII_CTL_SGMII_ENABLE_;
+ sgmii_ctl &= ~SGMII_CTL_SGMII_POWER_DN_;
+ lan743x_csr_write(adapter, SGMII_CTL, sgmii_ctl);
+ netif_info(adapter, drv, adapter->netdev, "SGMII operation\n");
+ } else {
+ sgmii_ctl = lan743x_csr_read(adapter, SGMII_CTL);
+ sgmii_ctl &= ~SGMII_CTL_SGMII_ENABLE_;
+ sgmii_ctl |= SGMII_CTL_SGMII_POWER_DN_;
+ lan743x_csr_write(adapter, SGMII_CTL, sgmii_ctl);
+ netif_info(adapter, drv, adapter->netdev, "GMII operation\n");
+ }
+ } else {
+ chip_ver = lan743x_csr_read(adapter, STRAP_READ);
+ netif_info(adapter, drv, adapter->netdev,
+ "ASIC Image version: 0x%08X\n", chip_ver);
+ if (chip_ver & STRAP_READ_SGMII_EN_) {
+ sgmii_ctl = lan743x_csr_read(adapter, SGMII_CTL);
+ sgmii_ctl |= SGMII_CTL_SGMII_ENABLE_;
+ sgmii_ctl &= ~SGMII_CTL_SGMII_POWER_DN_;
+ lan743x_csr_write(adapter, SGMII_CTL, sgmii_ctl);
+ netif_info(adapter, drv, adapter->netdev, "SGMII operation\n");
+ } else {
+ sgmii_ctl = lan743x_csr_read(adapter, SGMII_CTL);
+ sgmii_ctl &= ~SGMII_CTL_SGMII_ENABLE_;
+ sgmii_ctl |= SGMII_CTL_SGMII_POWER_DN_;
+ lan743x_csr_write(adapter, SGMII_CTL, sgmii_ctl);
+ netif_info(adapter, drv, adapter->netdev, "GMII operation\n");
+ }
+ }
+
adapter->mdiobus->priv = (void *)adapter;
adapter->mdiobus->read = lan743x_mdiobus_read;
adapter->mdiobus->write = lan743x_mdiobus_write;
diff --git a/drivers/net/ethernet/microchip/lan743x_main.h b/drivers/net/ethernet/microchip/lan743x_main.h
index 9c6bb8be2013..233555dd5464 100644
--- a/drivers/net/ethernet/microchip/lan743x_main.h
+++ b/drivers/net/ethernet/microchip/lan743x_main.h
@@ -29,6 +29,16 @@
#define FPGA_REV (0x04)
#define FPGA_REV_GET_MINOR_(fpga_rev) (((fpga_rev) >> 8) & 0x000000FF)
#define FPGA_REV_GET_MAJOR_(fpga_rev) ((fpga_rev) & 0x000000FF)
+#define FPGA_SGMII_OP BIT(24)
+
+#define STRAP_READ (0x0C)
+#define STRAP_READ_SGMII_EN_ BIT(6)
+#define STRAP_READ_SGMII_REFCLK_ BIT(5)
+#define STRAP_READ_SGMII_2_5G_ BIT(4)
+#define STRAP_READ_BASE_X_ BIT(3)
+#define STRAP_READ_RGMII_TXC_DELAY_EN_ BIT(2)
+#define STRAP_READ_RGMII_RXC_DELAY_EN_ BIT(1)
+#define STRAP_READ_ADV_PM_DISABLE_ BIT(0)
#define HW_CFG (0x010)
#define HW_CFG_RELOAD_TYPE_ALL_ (0x00000FC0)
@@ -218,6 +228,11 @@
#define MAC_WUCSR2 (0x600)
+#define SGMII_CTL (0x728)
+#define SGMII_CTL_SGMII_ENABLE_ BIT(31)
+#define SGMII_CTL_LINK_STATUS_SOURCE_ BIT(8)
+#define SGMII_CTL_SGMII_POWER_DN_ BIT(1)
+
#define INT_STS (0x780)
#define INT_BIT_DMA_RX_(channel) BIT(24 + (channel))
#define INT_BIT_ALL_RX_ (0x0F000000)
--
2.25.1
Powered by blists - more mailing lists