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Message-ID: <4524da71-3977-07db-bd6e-cebd1c539805@iogearbox.net> Date: Fri, 11 Feb 2022 15:39:48 +0100 From: Daniel Borkmann <daniel@...earbox.net> To: Hou Tao <houtao1@...wei.com>, Alexei Starovoitov <ast@...nel.org>, Mark Rutland <mark.rutland@....com> Cc: Martin KaFai Lau <kafai@...com>, Yonghong Song <yhs@...com>, Andrii Nakryiko <andrii@...nel.org>, Song Liu <songliubraving@...com>, "David S . Miller" <davem@...emloft.net>, John Fastabend <john.fastabend@...il.com>, netdev@...r.kernel.org, bpf@...r.kernel.org, Zi Shen Lim <zlim.lnx@...il.com>, Catalin Marinas <catalin.marinas@....com>, Will Deacon <will@...nel.org>, Julien Thierry <jthierry@...hat.com>, Ard Biesheuvel <ardb@...nel.org>, linux-arm-kernel@...ts.infradead.org Subject: Re: [PATCH bpf-next v3 2/4] arm64: insn: add encoders for atomic operations On 1/29/22 11:04 PM, Hou Tao wrote: > It is a preparation patch for eBPF atomic supports under arm64. eBPF > needs support atomic[64]_fetch_add, atomic[64]_[fetch_]{and,or,xor} and > atomic[64]_{xchg|cmpxchg}. The ordering semantics of eBPF atomics are > the same with the implementations in linux kernel. > > Add three helpers to support LDCLR/LDEOR/LDSET/SWP, CAS and DMB > instructions. STADD/STCLR/STEOR/STSET are simply encoded as aliases for > LDADD/LDCLR/LDEOR/LDSET with XZR as the destination register, so no extra > helper is added. atomic_fetch_add() and other atomic ops needs support for > STLXR instruction, so extend enum aarch64_insn_ldst_type to do that. > > LDADD/LDEOR/LDSET/SWP and CAS instructions are only available when LSE > atomics is enabled, so just return AARCH64_BREAK_FAULT directly in > these newly-added helpers if CONFIG_ARM64_LSE_ATOMICS is disabled. > > Signed-off-by: Hou Tao <houtao1@...wei.com> Hey Mark / Ard / Will / Catalin or others, could we get an Ack on patch 1 & 2 at min if it looks good to you? Thanks a lot, Daniel
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