netdev - Re: [PATCH net-next 5/6] net: dsa: qca8k: move pcs configuration

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Message-ID: <20220216154518.piewevdckvxhzkbe@skbuf>
Date:   Wed, 16 Feb 2022 17:45:18 +0200
From:   Vladimir Oltean <olteanv@...il.com>
To:     "Russell King (Oracle)" <rmk+kernel@...linux.org.uk>
Cc:     Ansuel Smith <ansuelsmth@...il.com>, Andrew Lunn <andrew@...n.ch>,
        "David S. Miller" <davem@...emloft.net>,
        Florian Fainelli <f.fainelli@...il.com>,
        Jakub Kicinski <kuba@...nel.org>, netdev@...r.kernel.org,
        Vivien Didelot <vivien.didelot@...il.com>
Subject: Re: [PATCH net-next 5/6] net: dsa: qca8k: move pcs configuration

On Wed, Feb 16, 2022 at 03:06:21PM +0000, Russell King (Oracle) wrote:
> @@ -1981,6 +1917,89 @@ static int qca8k_pcs_config(struct phylink_pcs *pcs, unsigned int mode,
>  			    const unsigned long *advertising,
>  			    bool permit_pause_to_mac)
>  {
> +	struct qca8k_priv *priv = pcs_to_qca8k_pcs(pcs)->priv;
> +	int cpu_port_index, ret, port;
> +	u32 reg, val;
> +
> +	port = pcs_to_qca8k_pcs(pcs)->port;
> +	switch (port) {
> +	case 0:
> +		reg = QCA8K_REG_PORT0_PAD_CTRL;
> +		cpu_port_index = QCA8K_CPU_PORT0;
> +		break;
> +
> +	case 6:
> +		reg = QCA8K_REG_PORT6_PAD_CTRL;
> +		cpu_port_index = QCA8K_CPU_PORT6;
> +		break;
> +
> +	default:
> +		WARN_ON(1);
> +	}
> +
> +	/* Enable/disable SerDes auto-negotiation as necessary */
> +	ret = qca8k_read(priv, QCA8K_REG_PWS, &val);
> +	if (ret)
> +		return ret;
> +	if (phylink_autoneg_inband(mode))
> +		val &= ~QCA8K_PWS_SERDES_AEN_DIS;
> +	else
> +		val |= QCA8K_PWS_SERDES_AEN_DIS;
> +	qca8k_write(priv, QCA8K_REG_PWS, val);
> +
> +	/* Configure the SGMII parameters */
> +	ret = qca8k_read(priv, QCA8K_REG_SGMII_CTRL, &val);
> +	if (ret)
> +		return ret;
> +
> +	val |= QCA8K_SGMII_EN_SD;
> +
> +	if (priv->ports_config.sgmii_enable_pll)
> +		val |= QCA8K_SGMII_EN_PLL | QCA8K_SGMII_EN_RX |
> +		       QCA8K_SGMII_EN_TX;
> +
> +	if (dsa_is_cpu_port(priv->ds, port)) {
> +		/* CPU port, we're talking to the CPU MAC, be a PHY */
> +		val &= ~QCA8K_SGMII_MODE_CTRL_MASK;
> +		val |= QCA8K_SGMII_MODE_CTRL_PHY;
> +	} else if (interface == PHY_INTERFACE_MODE_SGMII) {
> +		val &= ~QCA8K_SGMII_MODE_CTRL_MASK;
> +		val |= QCA8K_SGMII_MODE_CTRL_MAC;
> +	} else if (interface == PHY_INTERFACE_MODE_1000BASEX) {
> +		val &= ~QCA8K_SGMII_MODE_CTRL_MASK;
> +		val |= QCA8K_SGMII_MODE_CTRL_BASEX;
> +	}
> +
> +	qca8k_write(priv, QCA8K_REG_SGMII_CTRL, val);
> +
> +	/* From original code is reported port instability as SGMII also
> +	 * require delay set. Apply advised values here or take them from DT.
> +	 */
> +	if (interface == PHY_INTERFACE_MODE_SGMII)
> +		qca8k_mac_config_setup_internal_delay(priv, cpu_port_index, reg);
> +	/* For qca8327/qca8328/qca8334/qca8338 sgmii is unique and
> +	 * falling edge is set writing in the PORT0 PAD reg
> +	 */
> +	if (priv->switch_id == QCA8K_ID_QCA8327 ||
> +	    priv->switch_id == QCA8K_ID_QCA8337)
> +		reg = QCA8K_REG_PORT0_PAD_CTRL;
> +
> +	val = 0;
> +
> +	/* SGMII Clock phase configuration */
> +	if (priv->ports_config.sgmii_rx_clk_falling_edge)
> +		val |= QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE;
> +
> +	if (priv->ports_config.sgmii_tx_clk_falling_edge)
> +		val |= QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE;
> +
> +	if (val)
> +		ret = qca8k_rmw(priv, reg,
> +				QCA8K_PORT0_PAD_SGMII_RXCLK_FALLING_EDGE |
> +				QCA8K_PORT0_PAD_SGMII_TXCLK_FALLING_EDGE,
> +				val);
> +
> +

Would be nice to avoid two consecutive empty lines at the end.

>  	return 0;
>  }
>  
> -- 
> 2.30.2
>