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Message-ID: <Yh7jDF5CITerGkfF@lunn.ch>
Date: Wed, 2 Mar 2022 04:22:52 +0100
From: Andrew Lunn <andrew@...n.ch>
To: Arun Ramadoss <arun.ramadoss@...rochip.com>
Cc: netdev@...r.kernel.org, linux-kernel@...r.kernel.org,
Heiner Kallweit <hkallweit1@...il.com>,
Russell King <linux@...linux.org.uk>,
Jakub Kicinski <kuba@...nel.org>,
"David S . Miller" <davem@...emloft.net>
Subject: Re: [RFC PATCH net-next 3/4] net: phy: added the LAN937x phy support
On Mon, Feb 28, 2022 at 07:35:09PM +0530, Arun Ramadoss wrote:
> LAN937x T1 Phy is based on LAN87xx Phy, so reusing the init script of
> the Lan87xx. There is a workaround in accessing the DSP bank register
> for Lan937x Phy. Whenever there is a bank switch to DSP registers, then
> we need a dummy read access before proceeding to the actual register
> access.
>
> Signed-off-by: Prasanna Vengateshan <prasanna.vengateshan@...rochip.com>
> Signed-off-by: Arun Ramadoss <arun.ramadoss@...rochip.com>
> ---
> drivers/net/phy/microchip_t1.c | 47 +++++++++++++++++++++++++++++++---
> 1 file changed, 44 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/net/phy/microchip_t1.c b/drivers/net/phy/microchip_t1.c
> index 33325e5bd884..634a1423182a 100644
> --- a/drivers/net/phy/microchip_t1.c
> +++ b/drivers/net/phy/microchip_t1.c
> @@ -10,6 +10,7 @@
> #include <linux/ethtool_netlink.h>
>
> #define LAN87XX_PHY_ID 0x0007c150
> +#define LAN937X_T1_PHY_ID 0x0007c181
I guess the last 1 is meaningless, given the mask?
Andrew
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