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Date: Sat, 19 Mar 2022 13:19:21 +0200
From: Vladimir Oltean <olteanv@...il.com>
To: Tobias Waldekranz <tobias@...dekranz.com>
Cc: davem@...emloft.net, kuba@...nel.org,
Marek Behún <kabel@...nel.org>,
Andrew Lunn <andrew@...n.ch>,
Vivien Didelot <vivien.didelot@...il.com>,
Florian Fainelli <f.fainelli@...il.com>,
Paolo Abeni <pabeni@...hat.com>,
Russell King <linux@...linux.org.uk>, netdev@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH net-next] net: dsa: mv88e6xxx: Fill in STU support for
all supported chips
On Sat, Mar 19, 2022 at 12:03:45PM +0100, Tobias Waldekranz wrote:
> Some chips using the split VTU/STU design will not accept VTU entries
> who's SID points to an invalid STU entry. Therefore, mark all those
> chips with either the mv88e6352_g1_stu_* or mv88e6390_g1_stu_* ops as
> appropriate.
>
> Notably, chips for the Opal Plus (6085/6097) era seem to use a
> different implementation than those from Agate (6352) and onwards,
> even though their external interface is the same. The former happily
> accepts VTU entries referencing invalid STU entries, while the latter
> does not.
>
> This fixes an issue where the driver would fail to probe switch trees
> that contained chips of the Agate/Topaz generation which did not
> declare STU support, as loaded VTU entries would be read back as
> invalid.
>
> Fixes: 49c98c1dc7d9 ("net: dsa: mv88e6xxx: Disentangle STU from VTU")
> Reported-by: Marek Behún <kabel@...nel.org>
> Signed-off-by: Tobias Waldekranz <tobias@...dekranz.com>
> ---
Reviewed-by: Vladimir Oltean <olteanv@...il.com>
> drivers/net/dsa/mv88e6xxx/chip.c | 48 ++++++++++++++++++++++++++++++++
> 1 file changed, 48 insertions(+)
>
> diff --git a/drivers/net/dsa/mv88e6xxx/chip.c b/drivers/net/dsa/mv88e6xxx/chip.c
> index b36393ba6d49..34af6f46141f 100644
> --- a/drivers/net/dsa/mv88e6xxx/chip.c
> +++ b/drivers/net/dsa/mv88e6xxx/chip.c
> @@ -4064,6 +4064,8 @@ static const struct mv88e6xxx_ops mv88e6085_ops = {
> .rmu_disable = mv88e6085_g1_rmu_disable,
> .vtu_getnext = mv88e6352_g1_vtu_getnext,
> .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
> + .stu_getnext = mv88e6352_g1_stu_getnext,
> + .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
> .phylink_get_caps = mv88e6185_phylink_get_caps,
> .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
> };
> @@ -4184,6 +4186,8 @@ static const struct mv88e6xxx_ops mv88e6123_ops = {
> .atu_set_hash = mv88e6165_g1_atu_set_hash,
> .vtu_getnext = mv88e6352_g1_vtu_getnext,
> .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
> + .stu_getnext = mv88e6352_g1_stu_getnext,
> + .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
> .phylink_get_caps = mv88e6185_phylink_get_caps,
> .set_max_frame_size = mv88e6185_g1_set_max_frame_size,
> };
> @@ -4273,6 +4277,8 @@ static const struct mv88e6xxx_ops mv88e6141_ops = {
> .atu_set_hash = mv88e6165_g1_atu_set_hash,
> .vtu_getnext = mv88e6352_g1_vtu_getnext,
> .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
> + .stu_getnext = mv88e6352_g1_stu_getnext,
> + .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
> .serdes_power = mv88e6390_serdes_power,
> .serdes_get_lane = mv88e6341_serdes_get_lane,
> /* Check status register pause & lpa register */
> @@ -4329,6 +4335,8 @@ static const struct mv88e6xxx_ops mv88e6161_ops = {
> .atu_set_hash = mv88e6165_g1_atu_set_hash,
> .vtu_getnext = mv88e6352_g1_vtu_getnext,
> .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
> + .stu_getnext = mv88e6352_g1_stu_getnext,
> + .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
> .avb_ops = &mv88e6165_avb_ops,
> .ptp_ops = &mv88e6165_ptp_ops,
> .phylink_get_caps = mv88e6185_phylink_get_caps,
> @@ -4365,6 +4373,8 @@ static const struct mv88e6xxx_ops mv88e6165_ops = {
> .atu_set_hash = mv88e6165_g1_atu_set_hash,
> .vtu_getnext = mv88e6352_g1_vtu_getnext,
> .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
> + .stu_getnext = mv88e6352_g1_stu_getnext,
> + .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
> .avb_ops = &mv88e6165_avb_ops,
> .ptp_ops = &mv88e6165_ptp_ops,
> .phylink_get_caps = mv88e6185_phylink_get_caps,
> @@ -4409,6 +4419,8 @@ static const struct mv88e6xxx_ops mv88e6171_ops = {
> .atu_set_hash = mv88e6165_g1_atu_set_hash,
> .vtu_getnext = mv88e6352_g1_vtu_getnext,
> .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
> + .stu_getnext = mv88e6352_g1_stu_getnext,
> + .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
> .phylink_get_caps = mv88e6185_phylink_get_caps,
> };
>
> @@ -4455,6 +4467,8 @@ static const struct mv88e6xxx_ops mv88e6172_ops = {
> .atu_set_hash = mv88e6165_g1_atu_set_hash,
> .vtu_getnext = mv88e6352_g1_vtu_getnext,
> .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
> + .stu_getnext = mv88e6352_g1_stu_getnext,
> + .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
> .serdes_get_lane = mv88e6352_serdes_get_lane,
> .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
> .serdes_pcs_config = mv88e6352_serdes_pcs_config,
> @@ -4506,6 +4520,8 @@ static const struct mv88e6xxx_ops mv88e6175_ops = {
> .atu_set_hash = mv88e6165_g1_atu_set_hash,
> .vtu_getnext = mv88e6352_g1_vtu_getnext,
> .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
> + .stu_getnext = mv88e6352_g1_stu_getnext,
> + .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
> .phylink_get_caps = mv88e6185_phylink_get_caps,
> };
>
> @@ -4552,6 +4568,8 @@ static const struct mv88e6xxx_ops mv88e6176_ops = {
> .atu_set_hash = mv88e6165_g1_atu_set_hash,
> .vtu_getnext = mv88e6352_g1_vtu_getnext,
> .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
> + .stu_getnext = mv88e6352_g1_stu_getnext,
> + .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
> .serdes_get_lane = mv88e6352_serdes_get_lane,
> .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
> .serdes_pcs_config = mv88e6352_serdes_pcs_config,
> @@ -4651,6 +4669,8 @@ static const struct mv88e6xxx_ops mv88e6190_ops = {
> .atu_set_hash = mv88e6165_g1_atu_set_hash,
> .vtu_getnext = mv88e6390_g1_vtu_getnext,
> .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
> + .stu_getnext = mv88e6390_g1_stu_getnext,
> + .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
> .serdes_power = mv88e6390_serdes_power,
> .serdes_get_lane = mv88e6390_serdes_get_lane,
> /* Check status register pause & lpa register */
> @@ -4712,6 +4732,8 @@ static const struct mv88e6xxx_ops mv88e6190x_ops = {
> .atu_set_hash = mv88e6165_g1_atu_set_hash,
> .vtu_getnext = mv88e6390_g1_vtu_getnext,
> .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
> + .stu_getnext = mv88e6390_g1_stu_getnext,
> + .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
> .serdes_power = mv88e6390_serdes_power,
> .serdes_get_lane = mv88e6390x_serdes_get_lane,
> /* Check status register pause & lpa register */
> @@ -4771,6 +4793,8 @@ static const struct mv88e6xxx_ops mv88e6191_ops = {
> .atu_set_hash = mv88e6165_g1_atu_set_hash,
> .vtu_getnext = mv88e6390_g1_vtu_getnext,
> .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
> + .stu_getnext = mv88e6390_g1_stu_getnext,
> + .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
> .serdes_power = mv88e6390_serdes_power,
> .serdes_get_lane = mv88e6390_serdes_get_lane,
> /* Check status register pause & lpa register */
> @@ -4833,6 +4857,8 @@ static const struct mv88e6xxx_ops mv88e6240_ops = {
> .atu_set_hash = mv88e6165_g1_atu_set_hash,
> .vtu_getnext = mv88e6352_g1_vtu_getnext,
> .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
> + .stu_getnext = mv88e6352_g1_stu_getnext,
> + .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
> .serdes_get_lane = mv88e6352_serdes_get_lane,
> .serdes_pcs_get_state = mv88e6352_serdes_pcs_get_state,
> .serdes_pcs_config = mv88e6352_serdes_pcs_config,
> @@ -4933,6 +4959,8 @@ static const struct mv88e6xxx_ops mv88e6290_ops = {
> .atu_set_hash = mv88e6165_g1_atu_set_hash,
> .vtu_getnext = mv88e6390_g1_vtu_getnext,
> .vtu_loadpurge = mv88e6390_g1_vtu_loadpurge,
> + .stu_getnext = mv88e6390_g1_stu_getnext,
> + .stu_loadpurge = mv88e6390_g1_stu_loadpurge,
> .serdes_power = mv88e6390_serdes_power,
> .serdes_get_lane = mv88e6390_serdes_get_lane,
> /* Check status register pause & lpa register */
> @@ -5084,6 +5112,8 @@ static const struct mv88e6xxx_ops mv88e6341_ops = {
> .atu_set_hash = mv88e6165_g1_atu_set_hash,
> .vtu_getnext = mv88e6352_g1_vtu_getnext,
> .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
> + .stu_getnext = mv88e6352_g1_stu_getnext,
> + .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
> .serdes_power = mv88e6390_serdes_power,
> .serdes_get_lane = mv88e6341_serdes_get_lane,
> /* Check status register pause & lpa register */
> @@ -5144,6 +5174,8 @@ static const struct mv88e6xxx_ops mv88e6350_ops = {
> .atu_set_hash = mv88e6165_g1_atu_set_hash,
> .vtu_getnext = mv88e6352_g1_vtu_getnext,
> .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
> + .stu_getnext = mv88e6352_g1_stu_getnext,
> + .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
> .phylink_get_caps = mv88e6185_phylink_get_caps,
> };
>
> @@ -5186,6 +5218,8 @@ static const struct mv88e6xxx_ops mv88e6351_ops = {
> .atu_set_hash = mv88e6165_g1_atu_set_hash,
> .vtu_getnext = mv88e6352_g1_vtu_getnext,
> .vtu_loadpurge = mv88e6352_g1_vtu_loadpurge,
> + .stu_getnext = mv88e6352_g1_stu_getnext,
> + .stu_loadpurge = mv88e6352_g1_stu_loadpurge,
> .avb_ops = &mv88e6352_avb_ops,
> .ptp_ops = &mv88e6352_ptp_ops,
> .phylink_get_caps = mv88e6185_phylink_get_caps,
> @@ -5466,6 +5500,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
> .num_ports = 10,
> .num_internal_phys = 5,
> .max_vid = 4095,
> + .max_sid = 63,
> .port_base_addr = 0x10,
> .phy_base_addr = 0x0,
> .global1_addr = 0x1b,
> @@ -5532,6 +5567,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
> .num_ports = 3,
> .num_internal_phys = 5,
> .max_vid = 4095,
> + .max_sid = 63,
> .port_base_addr = 0x10,
> .phy_base_addr = 0x0,
> .global1_addr = 0x1b,
> @@ -5576,6 +5612,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
> .num_internal_phys = 5,
> .num_gpio = 11,
> .max_vid = 4095,
> + .max_sid = 63,
> .port_base_addr = 0x10,
> .phy_base_addr = 0x10,
> .global1_addr = 0x1b,
> @@ -5599,6 +5636,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
> .num_ports = 6,
> .num_internal_phys = 5,
> .max_vid = 4095,
> + .max_sid = 63,
> .port_base_addr = 0x10,
> .phy_base_addr = 0x0,
> .global1_addr = 0x1b,
> @@ -5623,6 +5661,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
> .num_ports = 6,
> .num_internal_phys = 0,
> .max_vid = 4095,
> + .max_sid = 63,
> .port_base_addr = 0x10,
> .phy_base_addr = 0x0,
> .global1_addr = 0x1b,
> @@ -5646,6 +5685,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
> .num_ports = 7,
> .num_internal_phys = 5,
> .max_vid = 4095,
> + .max_sid = 63,
> .port_base_addr = 0x10,
> .phy_base_addr = 0x0,
> .global1_addr = 0x1b,
> @@ -5670,6 +5710,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
> .num_internal_phys = 5,
> .num_gpio = 15,
> .max_vid = 4095,
> + .max_sid = 63,
> .port_base_addr = 0x10,
> .phy_base_addr = 0x0,
> .global1_addr = 0x1b,
> @@ -5693,6 +5734,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
> .num_ports = 7,
> .num_internal_phys = 5,
> .max_vid = 4095,
> + .max_sid = 63,
> .port_base_addr = 0x10,
> .phy_base_addr = 0x0,
> .global1_addr = 0x1b,
> @@ -5717,6 +5759,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
> .num_internal_phys = 5,
> .num_gpio = 15,
> .max_vid = 4095,
> + .max_sid = 63,
> .port_base_addr = 0x10,
> .phy_base_addr = 0x0,
> .global1_addr = 0x1b,
> @@ -5906,6 +5949,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
> .num_internal_phys = 5,
> .num_gpio = 15,
> .max_vid = 4095,
> + .max_sid = 63,
> .port_base_addr = 0x10,
> .phy_base_addr = 0x0,
> .global1_addr = 0x1b,
> @@ -5951,6 +5995,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
> .num_internal_phys = 9,
> .num_gpio = 16,
> .max_vid = 8191,
> + .max_sid = 63,
> .port_base_addr = 0x0,
> .phy_base_addr = 0x0,
> .global1_addr = 0x1b,
> @@ -6024,6 +6069,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
> .num_ports = 6,
> .num_gpio = 11,
> .max_vid = 4095,
> + .max_sid = 63,
> .port_base_addr = 0x10,
> .phy_base_addr = 0x10,
> .global1_addr = 0x1b,
> @@ -6048,6 +6094,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
> .num_ports = 7,
> .num_internal_phys = 5,
> .max_vid = 4095,
> + .max_sid = 63,
> .port_base_addr = 0x10,
> .phy_base_addr = 0x0,
> .global1_addr = 0x1b,
> @@ -6071,6 +6118,7 @@ static const struct mv88e6xxx_info mv88e6xxx_table[] = {
> .num_ports = 7,
> .num_internal_phys = 5,
> .max_vid = 4095,
> + .max_sid = 63,
> .port_base_addr = 0x10,
> .phy_base_addr = 0x0,
> .global1_addr = 0x1b,
> --
> 2.25.1
>
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