netdev - Re: [PATCH v4 3/4] dt-bindings: net: xilinx

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Date:   Tue, 22 Mar 2022 01:21:05 +0100
From:   Andrew Lunn <andrew@...n.ch>
To:     Rob Herring <robh@...nel.org>
Cc:     Radhey Shyam Pandey <radheys@...inx.com>,
        Andy Chiu <andy.chiu@...ive.com>,
        "robert.hancock@...ian.com" <robert.hancock@...ian.com>,
        Michal Simek <michals@...inx.com>,
        "davem@...emloft.net" <davem@...emloft.net>,
        "kuba@...nel.org" <kuba@...nel.org>,
        "pabeni@...hat.com" <pabeni@...hat.com>,
        "linux@...linux.org.uk" <linux@...linux.org.uk>,
        "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        Greentime Hu <greentime.hu@...ive.com>,
        Harini Katakam <harinik@...inx.com>
Subject: Re: [PATCH v4 3/4] dt-bindings: net: xilinx_axienet: add pcs-handle
 attribute

> > The use case is generic i.e. require separate handle to internal SGMII
> > and external Phy so would prefer this new DT convention is 
> > standardized or we discuss possible approaches on how to handle
> > both phys and not add it as vendor specific property in the first 
> > place.
> 
> IMO, you should use 'phys' for the internal PCS phy. That's aligned with 
> other uses like PCIe, SATA, etc. (there is phy h/w that will do PCS, 
> PCIe, SATA). 'phy-handle' is for the ethernet PHY.

We need to be careful here, because the PCS can have a well defined
set of registers accessible over MDIO. Generic PHY has no
infrastructure for that, it is all inside phylink which implements the
pcs registers which are part of 802.3.

I also wonder if a PCS might actually have a generic PHY embedded in
it to provide its lower interface?

   Andrew