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Date: Thu, 24 Mar 2022 02:00:18 +0800 From: Andy Chiu <andy.chiu@...ive.com> To: radhey.shyam.pandey@...inx.com, robert.hancock@...ian.com, michal.simek@...inx.com Cc: davem@...emloft.net, kuba@...nel.org, pabeni@...hat.com, robh+dt@...nel.org, linux@...linux.org.uk, andrew@...n.ch, netdev@...r.kernel.org, devicetree@...r.kernel.org, robh@...nel.org, Andy Chiu <andy.chiu@...ive.com> Subject: [PATCH v5 net 0/4] Fix broken link on Xilinx's AXI Ethernet in SGMII mode The Ethernet driver use phy-handle to reference the PCS/PMA PHY. This could be a problem if one wants to configure an external PHY via phylink, since it use the same phandle to get the PHY. To fix this, introduce a dedicated pcs-handle to point to the PCS/PMA PHY and deprecate the use of pointing it with phy-handle. A similar use case of pcs-handle can be seen on dpaa2 as well. The v4 patch was wrongly based on net-next tree. 1,2,4 parts of v5 patch was generated after re-applying the v4 patch then resolving conflicts on the net tree. 3/5 also describes the pcs-handle more globally at the ethernet-controller device tree binding document. Andy Chiu (4): net: axienet: setup mdio unconditionally net: axienet: factor out phy_node in struct axienet_local dt-bindings: net: add pcs-handle attribute net: axiemac: use a phandle to reference pcs_phy .../bindings/net/ethernet-controller.yaml | 6 ++++ .../bindings/net/xilinx_axienet.txt | 8 ++++- drivers/net/ethernet/xilinx/xilinx_axienet.h | 2 -- .../net/ethernet/xilinx/xilinx_axienet_main.c | 33 ++++++++++--------- 4 files changed, 31 insertions(+), 18 deletions(-) -- 2.34.1
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