netdev - sja1105q: proper way to solve PHY clk dependecy

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Message-ID: <20220323060331.GA4519@pengutronix.de>
Date:   Wed, 23 Mar 2022 07:03:31 +0100
From:   Oleksij Rempel <o.rempel@...gutronix.de>
To:     Vladimir Oltean <olteanv@...il.com>
Cc:     Andrew Lunn <andrew@...n.ch>,
        Vivien Didelot <vivien.didelot@...il.com>,
        Florian Fainelli <f.fainelli@...il.com>,
        "David S. Miller" <davem@...emloft.net>,
        Jakub Kicinski <kuba@...nel.org>,
        Yangbo Lu <yangbo.lu@....com>, netdev@...r.kernel.org,
        linux-kernel@...r.kernel.org, kernel@...gutronix.de
Subject: sja1105q: proper way to solve PHY clk dependecy

Hi Vladimir,

I have SJA1105Q based switch with 3 T1L PHYs connected over RMII
interface. The clk input "XI" of PHYs is connected to "MII0_TX_CLK/REF_CLK/TXC"
pins of the switch. Since this PHYs can't be configured reliably over MDIO
interface without running clk on XI input, i have a dependency dilemma:
i can't probe MDIO bus, without enabling DSA ports.

If I see it correctly, following steps should be done:
- register MDIO bus without scanning for PHYs
- define SJA1105Q switch as clock provider and PHYs as clk consumer
- detect and attach PHYs on port enable if clks can't be controlled
  without enabling the port.
- HW reset line of the PHYs should be asserted if we disable port and
  deasserted with proper reinit after port is enabled.

Other way would be to init and enable switch ports and PHYs by a bootloader and
keep it enabled.

What is the proper way to go?

Regards,
Oleksij
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