netdev - RE: [REGRESSION] Recent swiotlb DMA_FROM_DEVICE fixes break ath9k-based AP

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Message-ID: <273dec6267b249ca941558c268390fbc@AcuMS.aculab.com>
Date:   Fri, 25 Mar 2022 22:41:01 +0000
From:   David Laight <David.Laight@...LAB.COM>
To:     'Linus Torvalds' <torvalds@...ux-foundation.org>,
        Johannes Berg <johannes@...solutions.net>
CC:     Maxime Bizon <mbizon@...ebox.fr>,
        Toke Høiland-Jørgensen <toke@...e.dk>,
        Robin Murphy <robin.murphy@....com>,
        Christoph Hellwig <hch@....de>,
        Oleksandr Natalenko <oleksandr@...alenko.name>,
        Halil Pasic <pasic@...ux.ibm.com>,
        "Marek Szyprowski" <m.szyprowski@...sung.com>,
        Kalle Valo <kvalo@...nel.org>,
        "David S. Miller" <davem@...emloft.net>,
        Jakub Kicinski <kuba@...nel.org>,
        "Paolo Abeni" <pabeni@...hat.com>,
        Olha Cherevyk <olha.cherevyk@...il.com>,
        iommu <iommu@...ts.linux-foundation.org>,
        linux-wireless <linux-wireless@...r.kernel.org>,
        Netdev <netdev@...r.kernel.org>,
        "Linux Kernel Mailing List" <linux-kernel@...r.kernel.org>,
        Greg Kroah-Hartman <gregkh@...uxfoundation.org>,
        stable <stable@...r.kernel.org>
Subject: RE: [REGRESSION] Recent swiotlb DMA_FROM_DEVICE fixes break
 ath9k-based AP

From: Linus Torvalds
> Sent: 25 March 2022 21:57
> 
> On Fri, Mar 25, 2022 at 2:13 PM Johannes Berg <johannes@...solutions.net> wrote:
> >
> > Well I see now that you said 'cache "writeback"' in (1), and 'flush' in
> > (2), so perhaps you were thinking of the same, and I'm just calling it
> > "flush" and "invalidate" respectively?
> 
> Yeah, so I mentally tend to think of the operations as just
> "writeback" (which doesn't invalidate) and "flush" (which is a
> writeback-invalidate).

It almost certainly doesn't matter whether the "writeback"
invalidates or not.
You have to assume that all sorts of operations might cause
the cpu to read in a cacheline.
This includes, but is not limited to, speculative execution
and cache line prefetch.

But you definitely need an "invalidate" to force a cache line
be read after the hardware has accessed it.
Now such lines must not be dirty; because the cpu can write
back a dirty cache line at any time - which would break things.
So this can also be "write back if dirty" and "invalidate".

Bounce buffers and cache probably work much the same way.
But for bounce buffers I guess you want to ensure the initially
allocated buffer doesn't contain old data (belonging to
someone else).
So you might decide to zero them on allocation or always copy
from the driver buffer on the first request.

Then you get the really annoying cpu that don't have a 
"write back dirty line and invalidate" opcode.
And the only way is to read enough other memory areas
to displace all the existing cache line data.
You probably might as well give up and use PIO :-)

	David

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