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Message-Id: <20220329024921.2739338-1-andy.chiu@sifive.com>
Date: Tue, 29 Mar 2022 10:49:17 +0800
From: Andy Chiu <andy.chiu@...ive.com>
To: kuba@...nel.org, radhey.shyam.pandey@...inx.com,
robert.hancock@...ian.com, michal.simek@...inx.com, andrew@...n.ch
Cc: davem@...emloft.net, pabeni@...hat.com, robh+dt@...nel.org,
linux@...linux.org.uk, netdev@...r.kernel.org,
devicetree@...r.kernel.org, robh@...nel.org,
Andy Chiu <andy.chiu@...ive.com>
Subject: [PATCH v7 net 0/4] Fix broken link on Xilinx's AXI Ethernet in SGMII mode
The Ethernet driver use phy-handle to reference the PCS/PMA PHY. This
could be a problem if one wants to configure an external PHY via phylink,
since it use the same phandle to get the PHY. To fix this, introduce a
dedicated pcs-handle to point to the PCS/PMA PHY and deprecate the use
of pointing it with phy-handle. A similar use case of pcs-handle can be
seen on dpaa2 as well.
--- patch v5 ---
- Re-apply the v4 patch on the net tree.
- Describe the pcs-handle DT binding at ethernet-controller level.
--- patch v6 ---
- Remove "preferrably" to clearify usage of pcs_handle.
--- patch v7 ---
- Rebase the patch on latest net/master
Andy Chiu (4):
net: axienet: setup mdio unconditionally
net: axienet: factor out phy_node in struct axienet_local
dt-bindings: net: add pcs-handle attribute
net: axiemac: use a phandle to reference pcs_phy
.../bindings/net/ethernet-controller.yaml | 6 ++++
.../bindings/net/xilinx_axienet.txt | 8 ++++-
drivers/net/ethernet/xilinx/xilinx_axienet.h | 2 --
.../net/ethernet/xilinx/xilinx_axienet_main.c | 33 ++++++++++---------
4 files changed, 31 insertions(+), 18 deletions(-)
--
2.34.1
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