netdev - [PATCH 2/3] net: phy: adin: add support for 125MHz clk-out

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Date:   Sun, 10 Apr 2022 13:46:25 +0300
From:   Josua Mayer <josua@...id-run.com>
To:     netdev@...r.kernel.org
Cc:     alvaro.karsz@...id-run.com, Josua Mayer <josua@...id-run.com>,
        Michael Hennerich <michael.hennerich@...log.com>,
        Andrew Lunn <andrew@...n.ch>,
        Heiner Kallweit <hkallweit1@...il.com>,
        Russell King <linux@...linux.org.uk>,
        "David S. Miller" <davem@...emloft.net>,
        Jakub Kicinski <kuba@...nel.org>,
        Paolo Abeni <pabeni@...hat.com>
Subject: [PATCH 2/3] net: phy: adin: add support for 125MHz clk-out

The ADIN1300 supports generating certain clocks on its GP_CLK pin.
Add support for selecting the 125MHz clock via a device-tree property.

While other frequencies are technically available, they are omitted for
now, due to the complexity of choices.

Co-developed-by: Alvaro Karsz <alvaro.karsz@...id-run.com>
Signed-off-by: Alvaro Karsz <alvaro.karsz@...id-run.com>
Signed-off-by: Josua Mayer<josua@...id-run.com>
---
 drivers/net/phy/adin.c | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)

diff --git a/drivers/net/phy/adin.c b/drivers/net/phy/adin.c
index 5ce6da62cc8e..dbe2bb7f30d9 100644
--- a/drivers/net/phy/adin.c
+++ b/drivers/net/phy/adin.c
@@ -99,6 +99,10 @@
 #define ADIN1300_GE_SOFT_RESET_REG		0xff0c
 #define   ADIN1300_GE_SOFT_RESET		BIT(0)
 
+#define ADIN1300_GE_CLK_CFG_REG			0xff1f
+#define   ADIN1300_GE_CLK_CFG_MASK		GENMASK(5, 0)
+#define   ADIN1300_GE_CLK_CFG_FREE_125		BIT(4)
+
 #define ADIN1300_GE_RGMII_CFG_REG		0xff23
 #define   ADIN1300_GE_RGMII_RX_MSK		GENMASK(8, 6)
 #define   ADIN1300_GE_RGMII_RX_SEL(x)		\
@@ -433,6 +437,28 @@ static int adin_set_tunable(struct phy_device *phydev,
 	}
 }
 
+static int adin_config_clk_out(struct phy_device *phydev)
+{
+	struct device *dev = &phydev->mdio.dev;
+	u32 val;
+	u8 sel;
+
+	if (device_property_read_u32(dev, "adi,clk-out-frequency", &val))
+		return 0;
+
+	switch (val) {
+	case 125000000:
+		sel = ADIN1300_GE_CLK_CFG_FREE_125;
+		break;
+	default:
+		phydev_err(phydev, "invalid adi,clk-out-frequency\n");
+		return -EINVAL;
+	}
+
+	return phy_modify_mmd(phydev, MDIO_MMD_VEND1, ADIN1300_GE_CLK_CFG_REG,
+			      ADIN1300_GE_CLK_CFG_MASK, sel);
+}
+
 static int adin_config_init(struct phy_device *phydev)
 {
 	int rc;
@@ -455,6 +481,10 @@ static int adin_config_init(struct phy_device *phydev)
 	if (rc < 0)
 		return rc;
 
+	rc = adin_config_clk_out(phydev);
+	if (rc < 0)
+		return rc;
+
 	phydev_dbg(phydev, "PHY is using mode '%s'\n",
 		   phy_modes(phydev->interface));
 
-- 
2.34.1