netdev - Re: [PATCH net-next v1 1/4] net: phy: broadcom: Add PTP support for some Broadcom PHYs.

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite: Windows password security audit tool. GUI, reports in PDF.

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Mon, 25 Apr 2022 16:53:01 -0700
From:   Jonathan Lemon <jonathan.lemon@...il.com>
To:     Florian Fainelli <f.fainelli@...il.com>
Cc:     bcm-kernel-feedback-list@...adcom.com, andrew@...n.ch,
        hkallweit1@...il.com, linux@...linux.org.uk,
        richardcochran@...il.com, netdev@...r.kernel.org,
        kernel-team@...com
Subject: Re: [PATCH net-next v1 1/4] net: phy: broadcom: Add PTP support for
 some Broadcom PHYs.

On Sun, Apr 24, 2022 at 04:27:06PM -0700, Florian Fainelli wrote:
> 
> 
> On 4/23/2022 7:23 PM, Jonathan Lemon wrote:
> > This adds PTP support for BCM54210E Broadcom PHYs, in particular,
> > the BCM54213PE, as used in the Rasperry PI CM4.  It has only been
> > tested on that hardware.
> > 
> > Signed-off-by: Jonathan Lemon <jonathan.lemon@...il.com>
> > ---
> 
> [snip]
> 
> Mostly checking register names/offsets/usage because I am not familiar
> enough with how PTP is supposed to work.
> 
> > +#define MODE_SEL_SHIFT_PORT		0
> > +#define MODE_SEL_SHIFT_CPU		8
> > +
> > +#define rx_mode(sel, evt, act) \
> > +	(((MODE_RX_##act) << (MODE_EVT_SHIFT_##evt)) << (MODE_SEL_SHIFT_##sel))
> > +
> > +#define tx_mode(sel, evt, act) \
> > +	(((MODE_TX_##act) << (MODE_EVT_SHIFT_##evt)) << (MODE_SEL_SHIFT_##sel))
> 
> I would capitalize these two macros to make it clear that they are exactly
> that, macros.

Ack.


> > +/* needs global TS capture first */
> > +#define TX_TS_CAPTURE		0x0821
> > +#define  TX_TS_CAP_EN			BIT(0)
> > +#define RX_TS_CAPTURE		0x0822
> > +#define  RX_TS_CAP_EN			BIT(0)
> > +
> > +#define TIME_CODE_0		0x0854
> 
> Maybe add a macro here as well:
> 
> #define TIME_CODE(x)		(TIME_CODE0 + (x))

I'd prrefer keep them separate, as not all of the registers are
sequential - the heartbeat registers for example.


> > +#define SHADOW_LOAD		0x085d
> > +#define  TIME_CODE_LOAD			BIT(10)
> > +#define  SYNC_OUT_LOAD			BIT(9)
> > +#define  NCO_TIME_LOAD			BIT(7)
> 
> NCO Divider load is bit 8 and Local time Load bit is 7, can you check which
> one you need?

Local time load.  NCO divider counts the SYNC_IN pulses and generates a
timestamp after <n> events (as I understand things).

 
> > +#define  FREQ_LOAD			BIT(6)
> > +#define INTR_MASK		0x085e
> > +#define INTR_STATUS		0x085f
> > +#define  INTC_FSYNC			BIT(0)
> > +#define  INTC_SOP			BIT(1)
> > +
> > +#define FREQ_REG_LSB		0x0873
> > +#define FREQ_REG_MSB		0x0874
> 
> Those two hold the NCO frequency, can you rename accordingly?


> > +#define TS_READ_CTRL		0x0885
> > +#define  TS_READ_START			BIT(0)
> > +#define  TS_READ_END			BIT(1)
> > +
> > +#define TIMECODE_CTRL		0x08c3
> > +#define  TX_TIMECODE_SEL		GENMASK(7, 0)
> > +#define  RX_TIMECODE_SEL		GENMASK(15, 8)
> 
> This one looks out of order compared to the other registers

Will rearrange the groups a bit.


> > +struct bcm_ptp_private *bcm_ptp_probe(struct phy_device *phydev)
> > +{
> > +	struct bcm_ptp_private *priv;
> > +	struct ptp_clock *clock;
> > +
> > +	switch (BRCM_PHY_MODEL(phydev)) {
> > +	case PHY_ID_BCM54210E:
> > +#ifdef PHY_ID_BCM54213PE
> > +	case PHY_ID_BCM54213PE:
> > +#endif
> 
> This does not exist upstream.

Yes, hence the #ifdef.  Will remove this for the next patch.  It's here
since I can just copy it over to the rpi-5.15 tree and have it still
work.
-- 
Jonathan