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Message-ID: <20220427145617.0b36e9dc@fixe.home> Date: Wed, 27 Apr 2022 14:56:17 +0200 From: Clément Léger <clement.leger@...tlin.com> To: Geert Uytterhoeven <geert@...ux-m68k.org> Cc: Andrew Lunn <andrew@...n.ch>, Vivien Didelot <vivien.didelot@...il.com>, Florian Fainelli <f.fainelli@...il.com>, Vladimir Oltean <olteanv@...il.com>, "David S . Miller" <davem@...emloft.net>, Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>, Rob Herring <robh+dt@...nel.org>, Krzysztof Kozlowski <krzk+dt@...nel.org>, Magnus Damm <magnus.damm@...il.com>, Heiner Kallweit <hkallweit1@...il.com>, Russell King <linux@...linux.org.uk>, Thomas Petazzoni <thomas.petazzoni@...tlin.com>, Herve Codina <herve.codina@...tlin.com>, Miquèl Raynal <miquel.raynal@...tlin.com>, Milan Stevanovic <milan.stevanovic@...com>, Jimmy Lalande <jimmy.lalande@...com>, Linux Kernel Mailing List <linux-kernel@...r.kernel.org>, "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" <devicetree@...r.kernel.org>, Linux-Renesas <linux-renesas-soc@...r.kernel.org>, netdev <netdev@...r.kernel.org> Subject: Re: [PATCH net-next 05/12] dt-bindings: net: dsa: add bindings for Renesas RZ/N1 Advanced 5 port switch Le Wed, 27 Apr 2022 14:20:33 +0200, Geert Uytterhoeven <geert@...ux-m68k.org> a écrit : > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/net/dsa/renesas,rzn1-a5psw.yaml > > @@ -0,0 +1,128 @@ > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/net/dsa/renesas,rzn1-a5psw.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Renesas RZ/N1 Advanced 5 ports ethernet switch > > + > > +maintainers: > > + - Clément Léger <clement.leger@...tlin.com> > > + > > +description: | > > + The advanced 5 ports switch is present on the Renesas RZ/N1 SoC family and > > + handles 4 ports + 1 CPU management port. > > + > > +allOf: > > + - $ref: dsa.yaml# > > + > > +properties: > > + compatible: > > + const: renesas,rzn1-a5psw > > Please document an SoC-specific compatible value > "renesas,r9a06g032-a5psw", too, so we can easily handle differences > between members within the RZ/N1 family, if ever needed. Hi Geert, Thanks, I already did that for the V2 after your first comment on the MII converter bindings ! I'll sent a V2 soon. Clément > > Gr{oetje,eeting}s, > > Geert > > -- > Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@...ux-m68k.org > > In personal conversations with technical people, I call myself a hacker. But > when I'm talking to journalists I just say "programmer" or something like that. > -- Linus Torvalds -- Clément Léger, Embedded Linux and Kernel engineer at Bootlin https://bootlin.com
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