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Message-ID: <87levpzcds.fsf@tarshish> Date: Thu, 28 Apr 2022 13:59:55 +0300 From: Baruch Siach <baruch@...s.co.il> To: Marcin Wojtas <mw@...ihalf.com> Cc: Russell King <linux@...linux.org.uk>, netdev <netdev@...r.kernel.org> Subject: Re: [PATCH] net: mvpp2: add delay at the end of .mac_prepare Hi Marcin, On Thu, Apr 28 2022, Marcin Wojtas wrote: > śr., 27 kwi 2022 o 17:05 Baruch Siach <baruch@...s.co.il> napisał(a): >> >> From: Baruch Siach <baruch.siach@...lu.com> >> >> Without this delay PHY mode switch from XLG to SGMII fails in a weird >> way. Rx side works. However, Tx appears to work as far as the MAC is >> concerned, but packets don't show up on the wire. >> >> Tested with Marvell 10G 88X3310 PHY. >> >> Signed-off-by: Baruch Siach <baruch.siach@...lu.com> >> --- >> >> Not sure this is the right fix. Let me know if you have any better >> suggestion for me to test. >> >> The same issue and fix reproduce with both v5.18-rc4 and v5.10.110. >> --- >> drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c | 2 ++ >> 1 file changed, 2 insertions(+) >> >> diff --git a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c >>n index 1a835b48791b..8823efe396b1 100644 >> --- a/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c >> +++ b/drivers/net/ethernet/marvell/mvpp2/mvpp2_main.c >> @@ -6432,6 +6432,8 @@ static int mvpp2_mac_prepare(struct phylink_config *config, unsigned int mode, >> } >> } >> >> + mdelay(10); >> + >> return 0; >> } > > Thank you for the patch and debug effort, however at first glance it > seems that adding delay may be a work-around and cover an actual root > cause (maybe Russell will have more input here). That's my suspicion as well. > Can you share exact reproduction steps? I think I covered all relevant details. Is there anything you find missing? The hardware setup is very similar to the Macchiatobin Doubleshot. I can try to reproduce on that platform next week if it helps. The PHY MAC type (MV_V2_33X0_PORT_CTRL_MACTYPE_MASK) is set to MV_V2_33X0_PORT_CTRL_MACTYPE_10GBASER. I can add that DT phy-mode is set to "10gbase-kr" (equivalent to "10gbase-r" in this case). The port cp0_eth0 is connected to a 1G Ethernet switch. Kernel messages indicate that on interface up the MAC is first configured to XLG (10G), but after Ethernet (wire) auto-negotiation that MAC switches to SGMII. If I set DT phy-mode to "sgmii" the issue does not show. Same if I make a down/up cycle of the interface. Thanks for your review. baruch -- ~. .~ Tk Open Systems =}------------------------------------------------ooO--U--Ooo------------{= - baruch@...s.co.il - tel: +972.52.368.4656, http://www.tkos.co.il -
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