netdev - Re: [PATCH 1/2] dt-bindings: net: adin: document adi,clk_rcvr_125

lists.openwall.net		lists / announce owl-users owl-dev john-users john-dev passwdqc-users yescrypt popa3d-users / oss-security kernel-hardening musl sabotage tlsify passwords / crypt-dev xvendor / Bugtraq Full-Disclosure linux-kernel linux-netdev linux-ext4 linux-hardening linux-cve-announce PHC
Open Source and information security mailing list archives

Hash Suite for Android: free password hash cracker in your pocket

[<prev] [next>] [<thread-prev] [thread-next>] [day] [month] [year] [list]

Date:   Tue, 3 May 2022 13:50:48 +0200
From:   Krzysztof Kozlowski <krzysztof.kozlowski@...aro.org>
To:     Paolo Abeni <pabeni@...hat.com>, Nate Drude <nate.d@...iscite.com>,
        netdev@...r.kernel.org
Cc:     michael.hennerich@...log.com, eran.m@...iscite.com,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        devicetree@...r.kernel.org
Subject: Re: [PATCH 1/2] dt-bindings: net: adin: document adi,clk_rcvr_125_en
 property

On 02/05/2022 11:03, Paolo Abeni wrote:
> Hello,
> 
> On Fri, 2022-04-29 at 13:44 -0500, Nate Drude wrote:
>> Document device tree property to set GE_CLK_RCVR_125_EN (bit 5 of GE_CLK_CFG),
>> causing the 125 MHz PHY recovered clock (or PLL clock) to be driven at
>> the GP_CLK pin.
>>
>> Signed-off-by: Nate Drude <nate.d@...iscite.com>
>> ---
>>  Documentation/devicetree/bindings/net/adi,adin.yaml | 5 +++++
>>  1 file changed, 5 insertions(+)
>>
>> diff --git a/Documentation/devicetree/bindings/net/adi,adin.yaml b/Documentation/devicetree/bindings/net/adi,adin.yaml
>> index 1129f2b58e98..5fdbbd5aff82 100644
>> --- a/Documentation/devicetree/bindings/net/adi,adin.yaml
>> +++ b/Documentation/devicetree/bindings/net/adi,adin.yaml
>> @@ -36,6 +36,11 @@ properties:
>>      enum: [ 4, 8, 12, 16, 20, 24 ]
>>      default: 8
>>  
>> +  adi,clk_rcvr_125_en:

No underscores in node names

>> +    description: |
>> +      Set GE_CLK_RCVR_125_EN (bit 5 of GE_CLK_CFG), causing the 125 MHz
>> +      PHY recovered clock (or PLL clock) to be driven at the GP_CLK pin.

You are describing programming model but you should describe rather
hardware feature instead. This should be reflected in property name and
description. Focus on hardware and describe it.

>> +
>>  unevaluatedProperties: false
>>  
>>  examples:
> 
> The recipients list does not contain a few required ones, adding for
> awareness Rob, Krzysztof and the devicetree ML. If a new version should
> be required, please include them.

Thanks!

Nate,
Just please use scripts/get_maintainers.pl and all problems with
addressing are gone...


Best regards,
Krzysztof