netdev - RE: [PATCH 2/9] dt-bindings: net: renesas,etheravb: Document RZ/V2M SoC

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Date:   Mon, 9 May 2022 08:15:53 +0000
From:   Phil Edworthy <phil.edworthy@...esas.com>
To:     Sergey Shtylyov <s.shtylyov@....ru>,
        "David S. Miller" <davem@...emloft.net>,
        Eric Dumazet <edumazet@...gle.com>,
        Jakub Kicinski <kuba@...nel.org>,
        Paolo Abeni <pabeni@...hat.com>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>,
        Geert Uytterhoeven <geert+renesas@...der.be>
CC:     Sergei Shtylyov <sergei.shtylyov@...il.com>,
        "netdev@...r.kernel.org" <netdev@...r.kernel.org>,
        "linux-renesas-soc@...r.kernel.org" 
        <linux-renesas-soc@...r.kernel.org>,
        "devicetree@...r.kernel.org" <devicetree@...r.kernel.org>,
        Biju Das <biju.das.jz@...renesas.com>
Subject: RE: [PATCH 2/9] dt-bindings: net: renesas,etheravb: Document RZ/V2M
 SoC

Hi Sergey,

On 07 May 2022 19:21 Sergey Shtylyov wrote:
> On 5/4/22 5:54 PM, Phil Edworthy wrote:
> 
> > Document the Ethernet AVB IP found on RZ/V2M SoC.
> > It includes the Ethernet controller (E-MAC) and Dedicated Direct memory
> > access controller (DMAC) for transferring transmitted Ethernet frames
> > to and received Ethernet frames from respective storage areas in the
> > URAM at high speed.
> 
>    I think nobody knows what exactly URAM stands for... you better call it
> just RAM. :-)
Going point!

 
> > The AVB-DMAC is compliant with IEEE 802.1BA, IEEE 802.1AS timing and
> > synchronization protocol, IEEE 802.1Qav real-time transfer, and the
> > IEEE 802.1Qat stream reservation protocol.
> >
> > R-Car has a pair of combined interrupt lines:
> >  ch22 = Line0_DiA | Line1_A | Line2_A
> >  ch23 = Line0_DiB | Line1_B | Line2_B
> > Line0 for descriptor interrupts.
> > Line1 for error related interrupts (which we call err_a and err_b).
> > Line2 for management and gPTP related interrupts (mgmt_a and mgmt_b).
> >
> > RZ/V2M hardware has separate interrupt lines for each of these, but
> > we keep the "ch22" name for Line0_DiA.
> 
>    Not sure I agree here...
Ok, I'll use "dia" instead of ch22, and "line3" instead of ch24 on rz/v2m.
Is that ok?


>    BTW, aren't the interrupts called "Ethernet ABV.ch<n>" (as on R-Car
> gen3)
> in your (complete?) manual?
No, they are:
pif_intr_line_0_rx_n[0..17] for Line0_Rx[0..17] 
pif_intr_line_0_tx_n[0..3]  for Line0_Tx[0..3]
pif_intr_line_0_dia_n       for Line0_DiA
pif_intr_line_0_dib_n       for Line0_DiB
pif_intr_line_1_a_n         for Line1_A
pif_intr_line_1_b_n         for Line1_B
pif_intr_line_2_a_n         for Line2_A
pif_intr_line_2_b_n         for Line2_B
pif_intr_line_3_n           for Line3

The full HW manual is available, but an NDA is required:
https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-cortex-a-mpus/rzv2m-dual-cortex-a53-lpddr4x32bit-ai-accelerator-isp-4k-video-codec-4k-camera-input-fhd-display-output#document
"[NDA Required] RZ/V2M User's Manual: Hardware (Additional document)"


> > We also keep the "ch24" name for the Line3 (MAC) interrupt.
> >
> > It has 3 clocks; the main AXI clock, the AMBA CHI clock and a gPTP
> 
>    Could you spell out CHI like below?
Will do.


> > reference clock.
> >
> > Signed-off-by: Phil Edworthy <phil.edworthy@...esas.com>
> > Reviewed-by: Biju Das <biju.das.jz@...renesas.com>
> [...]

Thanks
Phil