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Message-ID: <SJ0PR18MB521639671BD7597B7CF6C0BDDBCF9@SJ0PR18MB5216.namprd18.prod.outlook.com>
Date:   Mon, 16 May 2022 04:45:37 +0000
From:   Suman Ghosh <sumang@...vell.com>
To:     Jakub Kicinski <kuba@...nel.org>
CC:     "davem@...emloft.net" <davem@...emloft.net>,
        "edumazet@...gle.com" <edumazet@...gle.com>,
        "pabeni@...hat.com" <pabeni@...hat.com>,
        Sunil Kovvuri Goutham <sgoutham@...vell.com>,
        Subbaraya Sundeep Bhatta <sbhatta@...vell.com>,
        Geethasowjanya Akula <gakula@...vell.com>,
        "Sunil.Goutham@...ium.com" <Sunil.Goutham@...ium.com>,
        Hariprasad Kelam <hkelam@...vell.com>,
        "colin.king@...el.com" <colin.king@...el.com>,
        "netdev@...r.kernel.org" <netdev@...r.kernel.org>
Subject: RE: [EXT] Re: [net-next PATCH] octeontx2-pf: Add support for adaptive
 interrupt coalescing

>You still claim this is tested? How can it work if you're not changing
>.supported_coalesce_params? Do we have a bug in the core?
[Suman] This feature is changing " cq_time_wait" and " cq_time_wait" dynamically based on net_dim. Which other .supported_coalesce_params do you mean?
>
>> +	/* Check and update coalesce status */
>> +	if ((pfvf->flags & OTX2_FLAG_ADPTV_INT_COAL_ENABLED) ==
>> +			OTX2_FLAG_ADPTV_INT_COAL_ENABLED) {
>> +		priv_coalesce_status = 1;
>> +		if (!ec->use_adaptive_rx_coalesce || !ec-
>>use_adaptive_tx_coalesce)
>> +			pfvf->flags &= ~OTX2_FLAG_ADPTV_INT_COAL_ENABLED;
>> +	} else {
>> +		priv_coalesce_status = 0;
>> +		if (ec->use_adaptive_rx_coalesce || ec-
>>use_adaptive_tx_coalesce)
>> +			pfvf->flags |= OTX2_FLAG_ADPTV_INT_COAL_ENABLED;
>> +	}
>
>Won't this flip-flop the flag? You should probably reject adaptive_rx !=
>adaptive_tx.
[Suman] The idea here is to enable/disable coalesce if either rx or tx status is enable/disable.
If we enable only adaptive_rx then adaptive_tx will also get enabled as for this hardware both RX and TX 
are mapped to the same queue. We do not support separate setting for rx/tx coalesce for a net-device.
>
>>  		/* Re-enable interrupts */
>>  		otx2_write64(pfvf, NIX_LF_CINTX_ENA_W1S(cq_poll->cint_idx),
>> -			     BIT_ULL(0));
>> +				BIT_ULL(0));
>
>Unrelated and possibly misalinged?
[Suman] Yes, will fix in V2.

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