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Date: Thu, 19 May 2022 20:50:56 +0200 From: Tommaso Merciai <tommaso.merciai@...rulasolutions.com> To: unlisted-recipients:; (no To-header on input) Cc: tommaso.merciai@...rulasolutions.com, michael@...rulasolutions.com, alberto.bianchi@...rulasolutions.com, linux-amarula@...rulasolutions.com, linuxfancy@...glegroups.com, Andrew Lunn <andrew@...n.ch>, Heiner Kallweit <hkallweit1@...il.com>, Russell King <linux@...linux.org.uk>, "David S. Miller" <davem@...emloft.net>, Eric Dumazet <edumazet@...gle.com>, Jakub Kicinski <kuba@...nel.org>, Paolo Abeni <pabeni@...hat.com>, netdev@...r.kernel.org, linux-kernel@...r.kernel.org Subject: [PATCH v2] net: phy: DP83822: enable rgmii mode if phy_interface_is_rgmii RGMII mode can be enable from dp83822 straps, and also writing bit 9 of register 0x17 - RMII and Status Register (RCSR). When phy_interface_is_rgmii rgmii mode must be enabled, same for contrary, this prevents malconfigurations of hw straps References: - https://www.ti.com/lit/gpn/dp83822i p66 Signed-off-by: Tommaso Merciai <tommaso.merciai@...rulasolutions.com> Co-developed-by: Michael Trimarchi <michael@...rulasolutions.com> Suggested-by: Alberto Bianchi <alberto.bianchi@...rulasolutions.com> Tested-by: Tommaso Merciai <tommaso.merciai@...rulasolutions.com> --- Changes since v1: - Improve commit msg - Add definition of bit 9 reg rcsr (rgmii mode en) - Handle case: phy_interface_is_rgmii is false drivers/net/phy/dp83822.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/drivers/net/phy/dp83822.c b/drivers/net/phy/dp83822.c index ce17b2af3218..7cb9d084707b 100644 --- a/drivers/net/phy/dp83822.c +++ b/drivers/net/phy/dp83822.c @@ -94,6 +94,9 @@ #define DP83822_WOL_INDICATION_SEL BIT(8) #define DP83822_WOL_CLR_INDICATION BIT(11) +/* RCSR bits */ +#define DP83822_RGMII_MODE_EN BIT(9) + /* RSCR bits */ #define DP83822_RX_CLK_SHIFT BIT(12) #define DP83822_TX_CLK_SHIFT BIT(11) @@ -408,6 +411,12 @@ static int dp83822_config_init(struct phy_device *phydev) if (err) return err; } + + phy_set_bits_mmd(phydev, DP83822_DEVADDR, + MII_DP83822_RCSR, DP83822_RGMII_MODE_EN); + } else { + phy_clear_bits_mmd(phydev, DP83822_DEVADDR, + MII_DP83822_RCSR, DP83822_RGMII_MODE_EN); } if (dp83822->fx_enabled) { -- 2.25.1
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