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Message-ID: <20220523065754.GJ1589864@tom-ThinkPad-T14s-Gen-2i>
Date: Mon, 23 May 2022 08:57:54 +0200
From: Tommaso Merciai <tommaso.merciai@...rulasolutions.com>
To: Andrew Lunn <andrew@...n.ch>
Cc: michael@...rulasolutions.com, alberto.bianchi@...rulasolutions.com,
linux-amarula@...rulasolutions.com, linuxfancy@...glegroups.com,
Heiner Kallweit <hkallweit1@...il.com>,
Russell King <linux@...linux.org.uk>,
"David S. Miller" <davem@...emloft.net>,
Eric Dumazet <edumazet@...gle.com>,
Jakub Kicinski <kuba@...nel.org>,
Paolo Abeni <pabeni@...hat.com>, netdev@...r.kernel.org,
linux-kernel@...r.kernel.org
Subject: Re: [PATCH v3] net: phy: DP83822: enable rgmii mode if
phy_interface_is_rgmii
On Sat, May 21, 2022 at 08:39:02PM +0200, Andrew Lunn wrote:
> On Sat, May 21, 2022 at 01:58:46AM +0200, Tommaso Merciai wrote:
> > RGMII mode can be enable from dp83822 straps, and also writing bit 9
> > of register 0x17 - RMII and Status Register (RCSR).
> > When phy_interface_is_rgmii rgmii mode must be enabled, same for
> > contrary, this prevents malconfigurations of hw straps
> >
> > References:
> > - https://www.ti.com/lit/gpn/dp83822i p66
> >
> > Signed-off-by: Tommaso Merciai <tommaso.merciai@...rulasolutions.com>
> > Co-developed-by: Michael Trimarchi <michael@...rulasolutions.com>
> > Suggested-by: Alberto Bianchi <alberto.bianchi@...rulasolutions.com>
> > Tested-by: Tommaso Merciai <tommaso.merciai@...rulasolutions.com>
>
> Reviewed-by: Andrew Lunn <andrew@...n.ch>
>
> If you want to, you could go further. If bit 9 is clear, bit 5 defines
> the mode, either RMII or MII. There are interface modes defined for
> these, so you could get bit 5 as well.
Hi Andrew,
Thanks for the review and for your time.
I'll try to go further, like you suggest :)
Regards,
Tommaso
>
> Andrew
--
Tommaso Merciai
Embedded Linux Engineer
tommaso.merciai@...rulasolutions.com
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