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Date: Fri, 17 Jun 2022 17:27:12 -0600 From: Rob Herring <robh@...nel.org> To: Sean Anderson <sean.anderson@...o.com> Cc: Eric Dumazet <edumazet@...gle.com>, Vinod Koul <vkoul@...nel.org>, netdev@...r.kernel.org, Rob Herring <robh+dt@...nel.org>, linux-kernel@...r.kernel.org, Paolo Abeni <pabeni@...hat.com>, devicetree@...r.kernel.org, linux-arm-kernel@...ts.infradead.org, Jakub Kicinski <kuba@...nel.org>, Russell King <linux@...linux.org.uk>, Kishon Vijay Abraham I <kishon@...com>, "David S . Miller" <davem@...emloft.net>, linux-phy@...ts.infradead.org, Krzysztof Kozlowski <krzysztof.kozlowski+dt@...aro.org>, Madalin Bucur <madalin.bucur@....com> Subject: Re: [PATCH net-next 01/28] dt-bindings: phy: Add QorIQ SerDes binding On Fri, 17 Jun 2022 16:32:45 -0400, Sean Anderson wrote: > This adds a binding for the SerDes module found on QorIQ processors. The > phy reference has two cells, one for the first lane and one for the > last. This should allow for good support of multi-lane protocols when > (if) they are added. There is no protocol option, because the driver is > designed to be able to completely reconfigure lanes at runtime. > Generally, the phy consumer can select the appropriate protocol using > set_mode. For the most part there is only one protocol controller > (consumer) per lane/protocol combination. The exception to this is the > B4860 processor, which has some lanes which can be connected to > multiple MACs. For that processor, I anticipate the easiest way to > resolve this will be to add an additional cell with a "protocol > controller instance" property. > > Each serdes has a unique set of supported protocols (and lanes). The > support matrix is stored in the driver and is selected based on the > compatible string. It is anticipated that a new compatible string will > need to be added for each serdes on each SoC that drivers support is > added for. > > There are two PLLs, each of which can be used as the master clock for > each lane. Each PLL has its own reference. For the moment they are > required, because it simplifies the driver implementation. Absent > reference clocks can be modeled by a fixed-clock with a rate of 0. > > Signed-off-by: Sean Anderson <sean.anderson@...o.com> > --- > > .../bindings/phy/fsl,qoriq-serdes.yaml | 78 +++++++++++++++++++ > 1 file changed, 78 insertions(+) > create mode 100644 Documentation/devicetree/bindings/phy/fsl,qoriq-serdes.yaml > My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check' on your patch (DT_CHECKER_FLAGS is new in v5.13): yamllint warnings/errors: dtschema/dtc warnings/errors: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/fsl,qoriq-serdes.example.dtb: phy@...0000: reg: [[0, 32112640], [0, 8192]] is too long From schema: /builds/robherring/linux-dt-review/Documentation/devicetree/bindings/phy/fsl,qoriq-serdes.yaml doc reference errors (make refcheckdocs): See https://patchwork.ozlabs.org/patch/ This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit.
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