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Date:   Fri, 24 Jun 2022 19:40:03 -0700
From:   Florian Fainelli <f.fainelli@...il.com>
To:     Clément Léger <clement.leger@...tlin.com>,
        Andrew Lunn <andrew@...n.ch>,
        Vivien Didelot <vivien.didelot@...il.com>,
        Vladimir Oltean <olteanv@...il.com>,
        "David S . Miller" <davem@...emloft.net>,
        Eric Dumazet <edumazet@...gle.com>,
        Jakub Kicinski <kuba@...nel.org>,
        Paolo Abeni <pabeni@...hat.com>,
        Rob Herring <robh+dt@...nel.org>,
        Krzysztof Kozlowski <krzk+dt@...nel.org>,
        Geert Uytterhoeven <geert+renesas@...der.be>,
        Magnus Damm <magnus.damm@...il.com>,
        Heiner Kallweit <hkallweit1@...il.com>,
        Russell King <linux@...linux.org.uk>,
        Alexandre Torgue <alexandre.torgue@...s.st.com>,
        Giuseppe Cavallaro <peppe.cavallaro@...com>,
        Jose Abreu <joabreu@...opsys.com>
Cc:     Thomas Petazzoni <thomas.petazzoni@...tlin.com>,
        Herve Codina <herve.codina@...tlin.com>,
        Miquèl Raynal <miquel.raynal@...tlin.com>,
        Milan Stevanovic <milan.stevanovic@...com>,
        Jimmy Lalande <jimmy.lalande@...com>,
        Pascal Eberhard <pascal.eberhard@...com>,
        linux-kernel@...r.kernel.org, devicetree@...r.kernel.org,
        linux-renesas-soc@...r.kernel.org, netdev@...r.kernel.org
Subject: Re: [PATCH net-next v9 15/16] ARM: dts: r9a06g032-rzn1d400-db: add
 switch description



On 6/24/2022 7:40 AM, Clément Léger wrote:
> Add description for the switch, GMAC2 and MII converter. With these
> definitions, the switch port 0 and 1 (MII port 5 and 4) are working on
> RZ/N1D-DB board.
> 
> Signed-off-by: Clément Léger <clement.leger@...tlin.com>
> Reviewed-by: Vladimir Oltean <olteanv@...il.com>
> ---

[snip]

> +	pinctrl-names = "default";
> +	pinctrl-0 = <&pins_mdio1>, <&pins_eth3>, <&pins_eth4>;
> +
> +	dsa,member = <0 0>;

Does not hurt to have it, but not required at this point. Not a reson to 
spin a v10 though:

Reviewed-by: Florian Fainelli <f.fainelli@...il.com>
-- 
Florian

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