netdev - Re: [RFC PATCH v2 1/3] dpll: Add DPLL framework base functions

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Message-Id: <20220629083439.6F5E3C34114@smtp.kernel.org>
Date:   Wed, 29 Jun 2022 01:34:37 -0700
From:   Stephen Boyd <sboyd@...nel.org>
To:     Arkadiusz Kubalewski <arkadiusz.kubalewski@...el.com>,
        Jakub Kicinski <kuba@...nel.org>,
        Jonathan Lemon <jonathan.lemon@...il.com>,
        Vadim Fedorenko <vfedorenko@...ek.ru>
Cc:     Vadim Fedorenko <vadfed@...com>, Aya Levin <ayal@...dia.com>,
        netdev@...r.kernel.org, linux-arm-kernel@...ts.infradead.org,
        linux-clk@...r.kernel.org
Subject: Re: [RFC PATCH v2 1/3] dpll: Add DPLL framework base functions

Quoting Vadim Fedorenko (2022-06-26 12:24:42)
> From: Vadim Fedorenko <vadfed@...com>
> 
> DPLL framework is used to represent and configure DPLL devices
> in systems. Each device that has DPLL and can configure sources
> and outputs can use this framework.

Please add more details to the commit text, and possibly introduce some
Documentation/ about this driver subsystem. I'm curious what is
different from drivers/clk/, is it super large frequencies that don't
fit into 32-bits when represented in Hz? Or PLL focused? Or is sub-Hz
required?

Details please!

Does DPLL stand for digital phase locked loop? Again, I have no idea! I
think you get my point.